BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be
used to allow the hypervisor to handle this intercept.

Add support to construct the required GHCB values to support a CPUID NAE
event. Additionally, CPUID 0x0000_000d (CPUID_EXTENDED_STATE) requires
XCR0 to be supplied in the GHCB, so add support to issue the XGETBV
instruction.

Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Ard Biesheuvel <ard.biesheu...@arm.com>
Acked-by: Laszlo Ersek <ler...@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
---
 OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 60 ++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c 
b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
index b74b13045cfd..1e0b2bf399da 100644
--- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
+++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
@@ -11,6 +11,7 @@
 #include <Library/BaseMemoryLib.h>

 #include <Library/VmgExitLib.h>

 #include <Register/Amd/Msr.h>

+#include <Register/Intel/Cpuid.h>

 #include <IndustryStandard/InstructionParsing.h>

 

 //

@@ -597,6 +598,61 @@ IoioExit (
   return 0;

 }

 

+/**

+  Handle a CPUID event.

+

+  Use the VMGEXIT instruction to handle a CPUID event.

+

+  @param[in, out] Ghcb             Pointer to the Guest-Hypervisor 
Communication

+                                   Block

+  @param[in, out] Regs             x64 processor context

+  @param[in]      InstructionData  Instruction parsing context

+

+  @return 0                        Event handled successfully

+  @return Others                   New exception value to propagate

+

+**/

+STATIC

+UINT64

+CpuidExit (

+  IN OUT GHCB                     *Ghcb,

+  IN OUT EFI_SYSTEM_CONTEXT_X64   *Regs,

+  IN     SEV_ES_INSTRUCTION_DATA  *InstructionData

+  )

+{

+  UINT64  Status;

+

+  Ghcb->SaveArea.Rax = Regs->Rax;

+  GhcbSetRegValid (Ghcb, GhcbRax);

+  Ghcb->SaveArea.Rcx = Regs->Rcx;

+  GhcbSetRegValid (Ghcb, GhcbRcx);

+  if (Regs->Rax == CPUID_EXTENDED_STATE) {

+    IA32_CR4  Cr4;

+

+    Cr4.UintN = AsmReadCr4 ();

+    Ghcb->SaveArea.XCr0 = (Cr4.Bits.OSXSAVE == 1) ? AsmXGetBv (0) : 1;

+    GhcbSetRegValid (Ghcb, GhcbXCr0);

+  }

+

+  Status = VmgExit (Ghcb, SVM_EXIT_CPUID, 0, 0);

+  if (Status != 0) {

+    return Status;

+  }

+

+  if (!GhcbIsRegValid (Ghcb, GhcbRax) ||

+      !GhcbIsRegValid (Ghcb, GhcbRbx) ||

+      !GhcbIsRegValid (Ghcb, GhcbRcx) ||

+      !GhcbIsRegValid (Ghcb, GhcbRdx)) {

+    return UnsupportedExit (Ghcb, Regs, InstructionData);

+  }

+  Regs->Rax = Ghcb->SaveArea.Rax;

+  Regs->Rbx = Ghcb->SaveArea.Rbx;

+  Regs->Rcx = Ghcb->SaveArea.Rcx;

+  Regs->Rdx = Ghcb->SaveArea.Rdx;

+

+  return 0;

+}

+

 /**

   Handle a #VC exception.

 

@@ -641,6 +697,10 @@ VmgExitHandleVc (
 

   ExitCode = Regs->ExceptionData;

   switch (ExitCode) {

+  case SVM_EXIT_CPUID:

+    NaeExit = CpuidExit;

+    break;

+

   case SVM_EXIT_IOIO_PROT:

     NaeExit = IoioExit;

     break;

-- 
2.27.0


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