Incorrect register is being set for configuring interrupt
priority. Correct register is located in SGI space and not
in RD space.
Signed-off-by: Ashish Singhal <ashishsin...@nvidia.com>
---
ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 8ef32b3..3c0bee6 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -236,7 +236,7 @@ ArmGicSetInterruptPriority (
}
MmioAndThenOr32 (
- GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
+ GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + (4
* RegOffset),
~(0xff << RegShift),
Priority << RegShift
);
--
2.7.4
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#72204): https://edk2.groups.io/g/devel/message/72204
Mute This Topic: https://groups.io/mt/80907153/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
