Arm's SMMUv3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe.
SMMUv3 also supports Address Translation Service (ATS) and Page
Request Interface (PRI) to work with PCIe devices.
ATS allows PCIe devices to request translation from a translation
agent such as SMMU, and then cache these translation in their private
cache called as Address Translation Cache (ATC).
Devices that support PRI can also enable the feature when ATS is
enabled as ATS is a prerequisite for PRI.
The I/O topology on SGI/RD platforms includes I/O devices (or PCIe
devices) connected to a SMMU-v3, and an GIC ITS block that facilitates
interrupt translations for message signaled interrupts. A typical view
of this topology is as below -
--------------- ------------ ------------
| PCIe device |---->| SMMUv3 |---->| ITS |
| (RequesterID) | | (StreamID) | | (DeviceID) |
--------------- ------------ ------------
This patch series adds the SMMU-v3 node in iort table, and sets up the
connection between these iort nodes to forward the traffic in the right
manner.
Changes since v1:
- Addressed review comments given by Sami:
- Replaced __builtin_offsetof() with OFFSET_OF() as suggested by Sami.
- Updated the commit message for patches.
Vivek Gautam (2):
Platform/Sgi: Add smmu-v3 node in the iort acpi table
Platform/Sgi: Enable ATS mode over PCI root complex
Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 60 ++++++++++++++++++--
1 file changed, 55 insertions(+), 5 deletions(-)
--
2.17.1
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