On 05/07/21 22:38, Brijesh Singh wrote: > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 > > Define the SEV-SNP MSR bits. > > Cc: James Bottomley <j...@linux.ibm.com> > Cc: Min Xu <min.m...@intel.com> > Cc: Jiewen Yao <jiewen....@intel.com> > Cc: Tom Lendacky <thomas.lenda...@amd.com> > Cc: Jordan Justen <jordan.l.jus...@intel.com> > Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org> > Cc: Laszlo Ersek <ler...@redhat.com> > Cc: Erdem Aktas <erdemak...@google.com> > Cc: Michael D Kinney <michael.d.kin...@intel.com> > Cc: Liming Gao <gaolim...@byosoft.com.cn> > Cc: Zhiguang Liu <zhiguang....@intel.com> > Signed-off-by: Brijesh Singh <brijesh.si...@amd.com> > --- > MdePkg/Include/Register/Amd/Fam17Msr.h | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h > b/MdePkg/Include/Register/Amd/Fam17Msr.h > index e4db09c5184c..716d52fd508d 100644 > --- a/MdePkg/Include/Register/Amd/Fam17Msr.h > +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h > @@ -87,7 +87,12 @@ typedef union { > /// > UINT32 SevEsBit:1; > > - UINT32 Reserved:30; > + /// > + /// [Bit 2] Secure Nested Paging (SevSnp) is enabled > + /// > + UINT32 SevSnpBit:1; > + > + UINT32 Reserved2:29; > } Bits; > /// > /// All bit fields as a 32-bit value >
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