Reviewed-by: Sai Chaganty <rangasai.v.chaga...@intel.com> -----Original Message----- From: Hsu, WesleyX <wesleyx....@intel.com> Sent: Thursday, July 29, 2021 12:23 AM To: devel@edk2.groups.io Cc: Hsu, WesleyX <wesleyx....@intel.com>; Chan, Amy <amy.c...@intel.com>; Yeh, HerbX <herbx....@intel.com>; Peng, NickX <nickx.p...@intel.com>; Ni, Ray <ray...@intel.com>; Chaganty, Rangasai V <rangasai.v.chaga...@intel.com> Subject: [PATCH v2] IntelSiliconPkg/VTd: Fix variables may be used uninitialized
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3491 Initialize several variables which may be used uninitialized after adding "-ffat-lto-objects" option in GCC5 tool chain. Change-Id: Ib2684aa70637d449f8bbddb18cf0a458a2742909 Signed-off-by: WesleyX Hsu <wesleyx....@intel.com> Cc: Amy Chan <amy.c...@intel.com> Cc: HerbX Yeh <herbx....@intel.com> Cc: NickX Peng <nickx.p...@intel.com> Cc: Ray Ni <ray...@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaga...@intel.com> --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c | 7 ++++++- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 9 +++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c index 341e2beb..6676b2a9 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat +++ ionTable.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2020 - 2021, Intel Corporation. All rights + reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -111,6 +111,11 @@ CreateSecondLevelPagingEntryTable ( return EFI_SUCCESS; } + Lvl4PagesStart = 0; + Lvl4PagesEnd = 0; + Lvl4PtEntry = NULL; + Lvl5PtEntry = NULL; + BaseAddress = ALIGN_VALUE_LOW (MemoryBase, SIZE_2MB); EndAddress = ALIGN_VALUE_UP (MemoryLimit, SIZE_2MB); DEBUG ((DEBUG_INFO, "CreateSecondLevelPagingEntryTable: BaseAddress - 0x%016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress)); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index d152039f..ca5f65a8 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT +++ able.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2017 - 2021, Intel Corporation. All rights + reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -133,7 +133,7 @@ CreateContextEntry ( mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE; if ((mAcpiDmarTable->HostAddressWidth <= 48) && ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) { - mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; + mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; } } else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) { DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported on VTD %d !!!!\n", VtdIndex)); @@ -199,6 +199,11 @@ CreateSecondLevelPagingEntryTable ( return EFI_SUCCESS; } + Lvl4PagesStart = 0; + Lvl4PagesEnd = 0; + Lvl4PtEntry = NULL; + Lvl5PtEntry = NULL; + BaseAddress = ALIGN_VALUE_LOW(MemoryBase, SIZE_2MB); EndAddress = ALIGN_VALUE_UP(MemoryLimit, SIZE_2MB); DEBUG ((DEBUG_INFO,"CreateSecondLevelPagingEntryTable: BaseAddress - 0x%016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress)); -- 2.32.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78372): https://edk2.groups.io/g/devel/message/78372 Mute This Topic: https://groups.io/mt/84528982/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-