On August 4, 2021 6:01 PM, Erdem Aktas wrote: > I agree with Brijesh on that this patch should be divided into smaller ones. In Brijesh's comments he will help to do following: 1. introduce the updated CcWorkArea structure 2. update the existing code to use the CcWorkArea layout Based on his patch, I will rework my patch. > > On Mon, Aug 2, 2021 at 6:18 PM Min Xu <min.m...@intel.com> wrote: > > > > + ; > > + ; EBP[6:0] CPU supported GPA width > > + ; > > + and ebp, 0x3f > > Based on > https://software.intel.com/content/dam/develop/external/us/en/documents > /tdx-module-1eas-v0.85.039.pdf > sec 8.1.2 > Is not this EBP[5:0] for GPA width ? it should be "and ebp, 0x1f" Ah, yes, it should be EBP[5:0] for GPA width. "and ebp, 0x3f" is correct. GPAW is in the lowest 6 bit. >
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