Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
-----Original Message-----
From: Oram, Isaac W <isaac.w.o...@intel.com>
Sent: Tuesday, October 19, 2021 8:00 PM
To: devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.o...@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desim...@intel.com>; Chiu, Chasel <chasel.c...@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2]
WhitleySiliconPkg/MultiPchPei: Open Source PEIM
Eliminate the need for the binary PEIM currenty in use by Whitley.
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Chasel Chiu <chasel.c...@intel.com>
Signed-off-by: Isaac Oram <isaac.w.o...@intel.com>
---
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPch.h
| 34 ++++++++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.c
| 84 ++++++++++++++++++++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
| 40 ++++++++++
3 files changed, 158 insertions(+)
diff --git
a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPch.h
b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPch.h
new file mode 100644
index 0000000000..1fe502b7a7
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Librar
+++ y/PchMultiPch.h
@@ -0,0 +1,34 @@
+/** @file
+ Prototype of the MultiPch library.
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_MULTI_PCH_LIB_H_
+#define _PCH_MULTI_PCH_LIB_H_
+
+#include <Ppi/PchPolicy.h>
+#include <Library/PchMultiPchBase.h>
+
+#define PCH_IP_INFO_REVISION 1
+
+typedef struct _PCH_IP_INFO {
+ /**
+ Revision 1: Original version
+ **/
+ UINT8 Revision;
+
+ BOOLEAN Valid[PCH_MAX];
+ UINT8 SocketId[PCH_MAX];
+ UINT8 Segment[PCH_MAX];
+ UINT8 Bus[PCH_MAX];
+ UINT64 P2sbBar[PCH_MAX];
+ UINT64 TempBar[PCH_MAX];
+ UINT64 PmcBar[PCH_MAX];
+ UINT64 SpiBar[PCH_MAX];
+} PCH_IP_INFO;
+
+#endif // _PCH_MULTI_PCH_LIB_H_
diff --git
a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.c
b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.c
new file mode 100644
index 0000000000..65cee5d031
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/M
+++ ultiPchPei.c
@@ -0,0 +1,84 @@
+/** @file
+ This driver manages the initial phase of Multi PCH
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <PiPei.h>
+#include <Uefi.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h> #include
+<Library/PchMultiPch.h>
+
+///
+/// The default PCH PCI segment number
+///
+#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0
+
+/**
+ @brief
+ Multi PCH entry point.
+
+ @param[in] FileHandle PEIM file handle @param[in] PeiServices General
+ purpose services available to every PEIM
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+MultiPchPeiEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PCH_IP_INFO *PchInfo;
+ EFI_PEI_PPI_DESCRIPTOR *PchIpInfoPpiDesc;
+
+ DEBUG ((DEBUG_INFO, "[PCH] MultiPchPeiEntryPoint called.\n"));
+
+ //
+ // Create PchIpInfo
+ //
+ PchInfo = (PCH_IP_INFO *) AllocateZeroPool (sizeof (PCH_IP_INFO));
+ if (PchInfo == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PchInfo->Revision = PCH_IP_INFO_REVISION;
+ PchInfo->Valid[PCH_LEGACY_ID] = TRUE; PchInfo->Segment[PCH_LEGACY_ID]
+ = DEFAULT_PCI_SEGMENT_NUMBER_PCH; PchInfo->Bus[PCH_LEGACY_ID] =
+ DEFAULT_PCI_BUS_NUMBER_PCH; PchInfo->P2sbBar[PCH_LEGACY_ID] =
+ PCH_PCR_BASE_ADDRESS; PchInfo->PmcBar[PCH_LEGACY_ID] =
+ PCH_PWRM_BASE_ADDRESS; PchInfo->SpiBar[PCH_LEGACY_ID] =
+ PCH_SPI_BASE_ADDRESS; PchInfo->TempBar[PCH_LEGACY_ID] =
+ PCH_TEMP_BASE_ADDRESS;
+
+ //
+ // Install PchIpInfoPpi
+ //
+ PchIpInfoPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool
+ (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (PchIpInfoPpiDesc == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ PchIpInfoPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ PchIpInfoPpiDesc->Guid = &gPchIpInfoPpiGuid;
+ PchIpInfoPpiDesc->Ppi = PchInfo;
+
+ Status = PeiServicesInstallPpi (PchIpInfoPpiDesc); if (EFI_ERROR
+ (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git
a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
new file mode 100644
index 0000000000..bd15593f2b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/M
+++ ultiPchPei.inf
@@ -0,0 +1,40 @@
+## @file
+# This driver manages the initial phase of Multi PCH # # @copyright #
+Copyright 2019 - 2021 Intel Corporation. <BR> # #
+SPDX-License-Identifier: BSD-2-Clause-Patent ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MultiPch
+ FILE_GUID = 0043A734-CB11-4274-B363-E165F958CB5F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = MultiPchPeiEntryPoint
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ MultiPchPei.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PeimEntryPoint
+ DebugLib
+
+[Ppis]
+ gPchIpInfoPpiGuid
+
+[Depex]
+ TRUE
--
2.27.0.windows.1
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