Signed-off-by: Abner Chang <abner.ch...@hpe.com>
Cc: Daniel Schaefer <daniel.schae...@hpe.com>
Cc: Sunil V L <suni...@ventanamicro.com>
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++--
.../FirmwareContextProcessorSpecificLib.inf | 2 +-
.../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 2 +-
.../Library/FirmwareContextProcessorSpecificLib.h | 4 ++--
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.h | 4 ++--
.../Edk2OpensbiPlatformWrapperLib.c | 10 +++++-----
.../FirmwareContextProcessorSpecificLib.c | 8 ++++----
.../PlatformBootManagerLib/PlatformBootManager.c | 4 ++--
.../Universal/Pei/PlatformPei/Platform.c | 4 ++--
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 10 +++++-----
Platform/RISC-V/PlatformPkg/Readme.md | 14 +++++++-------
.../PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 8 ++++----
12 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 53d424c901..f3217e4a05 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -1,7 +1,7 @@
## @file RiscVPlatformPkg.dec
# This Package provides UEFI RISC-V platform modules and libraries.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,7 +20,7 @@
[LibraryClasses]
FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
- Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h
+ Edk2OpensbiPlatformWrapperLib|Include/Library/Edk2OpensbiPlatformWrapperLib.h
[Guids]
gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6,
0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
diff --git
a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
index ea2550ce2c..8b645e2c5c 100644
---
a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+++
b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
@@ -1,6 +1,6 @@
## @file
# This is the library module of RISC-V EDK2 OpenSBI Firmware Context
-# Processor Specific hwardware information.
+# Processor Specific hardware information.
#
# Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
#
diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
index dc3a685d58..2579dafe86 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
@@ -1,7 +1,7 @@
## @file
# The FDT Peim driver is used to pass the device tree to DXE phase.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Developmente LP. All rights
reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git
a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
index 3920c61155..0eec62033b 100644
---
a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
+++
b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -1,7 +1,7 @@
/** @file
Firmware Context Processor-specific common library
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -18,7 +18,7 @@
@param FirmwareContextHartSpecific Pointer to
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
@param ParentProcessorGuid Pointer to GUID of Processor which
contains this core
- @param ParentProcessorUid Unique ID of pysical processor which
owns this core.
+ @param ParentProcessorUid Unique ID of physical processor which
owns this core.
@param CoreGuid Pointer to GUID of core
@param HartId Hart ID of this core.
@param IsBootHart This is boot hart or not
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 63a610fbd0..4098bd7d92 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -1,7 +1,7 @@
/** @file
RISC-V SEC phase module definitions..
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -35,7 +35,7 @@
**/
INT32
-SecPostOpenSbiPlatformEarlylInit(
+SecPostOpenSbiPlatformEarlyInit(
IN BOOLEAN ColdBoot
);
diff --git
a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
index 2137c6c619..0bd1b44241 100644
---
a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
+++
b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
@@ -1,7 +1,7 @@
/** @file
EDK2 OpenSBI generic platform wrapper library
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -43,7 +43,7 @@ SecSetEdk2FwMemoryRegions (
fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE |
SBI_DOMAIN_MEMREGION_READABLE;
Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion
*)&fw_memregs);
if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n",
__FUNCTION__));
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of FW Domain fail\n",
__FUNCTION__));
}
//
@@ -54,7 +54,7 @@ SecSetEdk2FwMemoryRegions (
fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE |
SBI_DOMAIN_MEMREGION_WRITEABLE;
Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion
*)&fw_memregs);
if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain
fail\n", __FUNCTION__));
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of variable FW Domain
fail\n", __FUNCTION__));
}
return Ret;
}
@@ -66,7 +66,7 @@ SecSetEdk2FwMemoryRegions (
**/
INT32
-SecPostOpenSbiPlatformEarlylInit(
+SecPostOpenSbiPlatformEarlyInit(
IN BOOLEAN ColdBoot
)
{
@@ -190,7 +190,7 @@ Edk2OpensbiPlatformEarlyInit (
}
}
if (ColdBoot) {
- return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
+ return SecPostOpenSbiPlatformEarlyInit(ColdBoot);
}
return 0;
}
diff --git
a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
index 143c18d62c..c94f7881c2 100644
---
a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
+++
b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -1,7 +1,7 @@
/** @file
- Common library to build upfirmware context processor-specific information
+ Common library to build up firmware context processor-specific information
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -28,7 +28,7 @@
@param FirmwareContextHartSpecific Pointer to
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
@param ParentProcessorGuid Pointer to GUID of Processor which
contains this core
- @param ParentProcessorUid Unique ID of pysical processor which
owns this core.
+ @param ParentProcessorUid Unique ID of physical processor which
owns this core.
@param CoreGuid Pointer to GUID of core
@param HartId Hart ID of this core.
@param IsBootHart This is boot hart or not
@@ -52,7 +52,7 @@ CommonFirmwareContextHartSpecificInfo (
//
// Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
//
- CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid,
ParentProcessorGuid);
+ CopyGuid (&ProcessorSpecificDataHob->ParentProcessorGuid,
ParentProcessorGuid);
ProcessorSpecificDataHob->ParentProcessorUid = ParentProcessorUid;
CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);
ProcessorSpecificDataHob->Context = NULL;
diff --git
a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
index deaad7d5a1..9ad4ef17db 100644
---
a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++
b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -1,7 +1,7 @@
/** @file
This file include all platform actions
-Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -215,7 +215,7 @@ PlatformBootManagerBeforeConsole (
Signal console ready platform customized event;
Run diagnostics like memory testing;
Connect certain devices;
- Dispatch aditional option roms.
+ Dispatch additional option roms.
**/
VOID
EFIAPI
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index 972a429fb9..c28b2ed373 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -296,7 +296,7 @@ BootModeInitialization (
{
EFI_STATUS Status;
- if (CheckResumeFromS3 ()) {
+ if (CheckResumeFromS3) {
DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
} else {
DEBUG ((DEBUG_INFO, "This is normal boot\n"));
@@ -357,7 +357,7 @@ InitializePlatform (
MiscInitialization ();
Status = BuildCoreInformationHob ();
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
+ DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));
ASSERT(FALSE);
}
return EFI_SUCCESS;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 1fafed2799..7a79eeec2d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -291,7 +291,7 @@ FindPeiCoreImageBase (
/**
Find and return Pei Core entry point.
- It also find SEC and PEI Core file debug inforamtion. It will report them if
+ It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param[in] BootFirmwareVolumePtr The firmware volume pointer to search
@@ -516,7 +516,7 @@ LaunchPeiCore (
@param[in] FuncArg1 Arg1 to pass to next phase entry point address.
@param[in] NextAddr Entry point of next phase.
@param[in] NextMode Privilege mode of next phase.
- @param[in] NextVirt Next phase is in virtualiztion.
+ @param[in] NextVirt Next phase is in virtualization.
**/
VOID
@@ -600,7 +600,7 @@ Edk2PlatformHartIndex2Id (
}
/**
- This function initilizes hart specific information and SBI.
+ This function initializes hart specific information and SBI.
For the boot hart, it boots system through PEI core and initial SBI in the
DXE IPL.
For others, it goes to initial SBI and halt.
@@ -658,9 +658,9 @@ SecCoreStartUpWithStack(
HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
//
- // Hook platorm_ops with EDK2 one. Thus we can have interface
+ // Hook platform_ops with EDK2 one. Thus we can have interface
// call out to OEM EDK2 platform code in M-mode before switching
- // to S-mode in opensbo init.
+ // to S-mode in opensbi init.
//
ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
diff --git a/Platform/RISC-V/PlatformPkg/Readme.md
b/Platform/RISC-V/PlatformPkg/Readme.md
index 66fba15544..5a344a864a 100644
--- a/Platform/RISC-V/PlatformPkg/Readme.md
+++ b/Platform/RISC-V/PlatformPkg/Readme.md
@@ -26,16 +26,16 @@ differently from the default settings according to the OEM
platform design.
to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib***
provides the RISC-V SBI
implementation and initialize the OpenSBI boot flow. SEC module is also linked
with below libraries,
- edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that provides
the generic RISC-V platform initialization code.
-- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) library
which is provided by the RISC-V
+- edk2 [RiscVSpecialPlatformLib](#RiscVSpecialPlatformLib-library) library
which is provided by the RISC-V
platform vendor for the platform-specific initialization. The underlying
implementation of above two edk2 libraries
are from OpenSBI project. edk2 libraries are introduced as the wrapper
libraries that separates and organizes OpenSBI core and platform code based on
edk2 framework and the the build mechanism for edk2 RISC-V platforms.
***RiscVOpensbiLib*** library is located under [RISC-V
ProcessorPkg](https://github.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg)
while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V
PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platform/RISC-V/PlatformPkg).
-- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is
provided by the platform vendor and located under edk2 RISC-V platform-specific
folder.
+- edk2 [RiscVSpecialPlatformLib](#riscvspecialplatformlib) library is provided
by the platform vendor and located under edk2 RISC-V platform-specific folder.
##### OpenSbiPlatformLib Library
[Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams)
> ***OpenSbiPlatformLib*** provides the generic RISC-V platform initialization
> code. Platform vendor can just utilize this library if they don't have
> additional requirements on the platform initialization.
-##### RiscVSpecifialPlatformLib Library
+##### RiscVSpecialPlatformLib Library
[Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams)
> The major use case of this library is to facilitate the interfaces for
> platform vendors to provide the special
platform initialization based on the generic platform initialization library.
@@ -57,7 +57,7 @@ privilege according to the PCD.
#### PEI Phase
SEC module hands off the boot process to PEI core in the privilege configured
by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is forced
to S-mode)*. PEI and later phases are allowed to executed in M-mode
-if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode)
for the virtualization. RISC-V edk2 port provides its own instance
***PeiCoreEntryPoint*** library [(indicated as #7 in the
figure)](#risc-v-edk2-port-design-diagrams) and linked with
[PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode
PEI phase. PEI core requires
[RiscVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve
the information of RISC-V HARTs and platform (e.g. FDT) configurations that
built up in SEC phase. ***PeiServicePointer*** is also maintained in the
***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by
[PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
+if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode)
for the virtualization. RISC-V edk2 port provides its own instance
***PeiCoreEntryPoint*** library [(indicated as #7 in the
figure)](#risc-v-edk2-port-design-diagrams) and linked with
[PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode
PEI phase. PEI core requires
[RiscVFirmwareContextLib](#riscvfirmwarecontextlib-library) library to retrieve
the information of RISC-V HARTs and platform (e.g. FDT) configurations that
built up in SEC phase. ***PeiServicePointer*** is also maintained in the
***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by
[PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
##### PlatformSecPpiLib Library
[Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams)
@@ -178,7 +178,7 @@ The PCD settings regard to EFI Variable
|PcdVariableFdSize| The EFI variable firmware device size|
|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within
firmware device|
-|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable
fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable
fault tolerance workspace (FTW) within firmware device|
|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare
FTW within firmware device|
### RISC-V Physical Memory Protection (PMP) Region Settings
@@ -190,7 +190,7 @@ Below PCDs could be set in platform FDF file.
|PcdRootFirmwareDomainSize| The size of root firmware domain|-|-|
|PcdFirmwareDomainBaseAddress| The starting address of firmware domain that
can be accessed and executed in S-mode|Full access|Readable and Executable|
|PcdFirmwareDomainSize| The size of firmware domain|-|-|
-|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable
region that can be accessed in S-mode|Full access|Readale and Writable|
+|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable
region that can be accessed in S-mode|Full access|Readable and Writable|
|PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-|-|
### RISC-V Processor HART Settings
@@ -198,7 +198,7 @@ Below PCDs could be set in platform FDF file.
| **PCD name** |**Usage**|
|--------------|---------|
|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation
specific|
-|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot
system to OS|
+|PcdBootHartId| The ID of RISC-V HART to execute main firmware code and boot
system to OS|
|PcdBootableHartNumber|The bootable HART number, which is incorporate with
RISC-V OpenSBI platform hart_index2id value|
|PcdBootableHartIndexToId| if PcdBootableHartNumber == 0, hart_index2id is
built from Device Tree, otherwise this is an array of HART index to HART ID|
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 0fc7817665..a96dd9474b 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -67,7 +67,7 @@ skip_fw_init:
* DTB for this processor. We allocate the
* scratch buffer according to this number.
*/
- la a4, _pysical_hart_count
+ la a4, _physical_hart_count
sd s7, (a4)
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
@@ -227,7 +227,7 @@ _start_warm:
csrr a0, CSR_MHARTID
j _uninitialized_hart_wait
4:
- la a5, _pysical_hart_count
+ la a5, _physical_hart_count
ld s7, (a5)
/* Find the scratch space for this hart
*
@@ -294,7 +294,7 @@ _start_warm:
.section .data, "aw"
_boot_hart_done:
RISCV_PTR 0
-_pysical_hart_count:
+_physical_hart_count:
RISCV_PTR 0
.align 3
@@ -323,7 +323,7 @@ _hartid_to_scratch:
lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
#endif
- la s1, _pysical_hart_count /* total HART count */
+ la s1, _physical_hart_count /* total HART count */
ld s2, (s1)
mul s2, s2, s0
li s1, FixedPcdGet32 (PcdScratchRamBase)
--
2.31.1
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