There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib.
Cc: Michael D Kinney <michael.d.kin...@intel.com> Cc: Liming Gao <gaolim...@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang....@intel.com> Signed-off-by: Yu Pu <yu...@intel.com> --- MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c | 75 ++++++++++++++++++++ MdePkg/Include/Library/CpuLib.h | 48 +++++++++++++ MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 ++ MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm | 68 ++++++++++++++++++ MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm | 51 +++++++++++++ 5 files changed, 248 insertions(+) diff --git a/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c b/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c new file mode 100644 index 000000000000..e69f00417022 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c @@ -0,0 +1,75 @@ +/** @file + This library defines some routines that are generic for IA32 family CPU. + The library routines are UEFI specification compliant. + Copyright (c) 2020, AMD Inc. All rights reserved.<BR> + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Register/Intel/Cpuid.h> +#include <Register/Amd/Cpuid.h> + +#include <Library/BaseLib.h> +#include <Library/CpuLib.h> + +/** + Determine if the standard CPU signature is "AuthenticAMD". + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ) +{ + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); +} + +/** + Return the 32bit CPU family and model value. + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. +**/ +UINT32 +EFIAPI +GetCpuFamilyModel ( + VOID + ) +{ + CPUID_VERSION_INFO_EAX Eax; + + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); + + // + // Mask other fields than Family and Model. + // + Eax.Bits.SteppingId = 0; + Eax.Bits.ProcessorType = 0; + Eax.Bits.Reserved1 = 0; + Eax.Bits.Reserved2 = 0; + return Eax.Uint32; +} + +/** + Return the CPU stepping ID. + @return CPU stepping ID value in CPUID[01h].EAX. +**/ +UINT8 +EFIAPI +GetCpuSteppingId ( + VOID + ) +{ + CPUID_VERSION_INFO_EAX Eax; + + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); + + return (UINT8)Eax.Bits.SteppingId; +} diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLib.h index 25f6d9478c52..3f29937dc71b 100644 --- a/MdePkg/Include/Library/CpuLib.h +++ b/MdePkg/Include/Library/CpuLib.h @@ -41,4 +41,52 @@ CpuFlushTlb ( VOID ); +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) + +/** + Initializes floating point units for requirement of UEFI specification. + This function initializes floating-point control word to 0x027F (all exceptions + masked,double-precision, round-to-nearest) and multimedia-extensions control word + (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero + for masked underflow). +**/ +VOID +EFIAPI +InitializeFloatingPointUnits ( + VOID + ); + +/** + Determine if the standard CPU signature is "AuthenticAMD". + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ); + +/** + Return the 32bit CPU family and model value. + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. +**/ +UINT32 +EFIAPI +GetCpuFamilyModel ( + VOID + ); + +/** + Return the CPU stepping ID. + @return CPU stepping ID value in CPUID[01h].EAX. +**/ +UINT8 +EFIAPI +GetCpuSteppingId ( + VOID + ); + +#endif + #endif diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf index 950f5229b2a4..7cdbb552c08c 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -28,6 +28,9 @@ # VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 # +[Sources.IA32, Sources.X64] + X86BaseCpuLib.c + [Sources.IA32] Ia32/CpuSleep.c | MSFT Ia32/CpuFlushTlb.c | MSFT @@ -38,10 +41,13 @@ Ia32/CpuSleepGcc.c | GCC Ia32/CpuFlushTlbGcc.c | GCC + Ia32/InitializeFpu.nasm + [Sources.X64] X64/CpuFlushTlb.nasm X64/CpuSleep.nasm + X64/InitializeFpu.nasm [Sources.EBC] Ebc/CpuSleepFlushTlb.c diff --git a/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm b/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm new file mode 100644 index 000000000000..5e27cc325012 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm @@ -0,0 +1,68 @@ +;------------------------------------------------------------------------------ +;* +;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR> +;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;------------------------------------------------------------------------------ + + SECTION .rodata + +; +; Float control word initial value: +; all exceptions masked, double-precision, round-to-nearest +; +mFpuControlWord: DW 0x27F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underflow +; +mMmxControlWord: DD 0x1F80 + + SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exceptions +; masked,double-precision, round-to-nearest) and multimedia-extensions control word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero +; for masked underflow). +; +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + push ebx + + ; + ; Initialize floating point units + ; + finit + fldcw [mFpuControlWord] + + ; + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test + ; whether the processor supports SSE instruction. + ; + mov eax, 1 + cpuid + bt edx, 25 + jnc Done + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov eax, cr4 + or eax, BIT9 + mov cr4, eax + + ; + ; The processor should support SSE instruction and we can use + ; ldmxcsr instruction + ; + ldmxcsr [mMmxControlWord] +Done: + pop ebx + + ret + diff --git a/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm b/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm new file mode 100644 index 000000000000..8485b4713548 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm @@ -0,0 +1,51 @@ +;------------------------------------------------------------------------------ +;* +;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR> +;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;------------------------------------------------------------------------------ + + SECTION .rodata +; +; Float control word initial value: +; all exceptions masked, double-extended-precision, round-to-nearest +; +mFpuControlWord: DW 0x37F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underflow +; +mMmxControlWord: DD 0x1F80 + +DEFAULT REL +SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exceptions +; masked,double-precision, round-to-nearest) and multimedia-extensions control word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero +; for masked underflow). +; +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + ; + ; Initialize floating point units + ; + finit + fldcw [mFpuControlWord] + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov rax, cr4 + or rax, BIT9 + mov cr4, rax + + ldmxcsr [mMmxControlWord] + + ret + -- 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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