Hi Ard, Leif,
On Tue, 10 May 2022 at 17:25, Masahisa Kojima via groups.io
<masahisa.kojima=linaro....@groups.io> wrote:
>
> From: Kazuhiko Sakamoto <sakamoto.kazuh...@socionext.com>
>
> Support 4-bytes address for erase and write, so that we can
> access whole region of SPI-NOR Flash(64MiB) implemented on the
> Developerbox.
>
> This commit also fixes the wrong macro name. SPINOR_OP_SE and
> SPINOR_OP_SE_4B is the commoand for 64KB block erase,
> it must be SPINOR_OP_BE and SPINOR_OP_BE_4B.
>
> Signed-off-by: Masahisa Kojima <masahisa.koj...@linaro.org>
> ---
> Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h | 4 ++--
> Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c | 13 +++++--------
> 2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> index bade5706e6ae..3cb86ab588e0 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> @@ -313,7 +313,7 @@ NorFlashReadID (
> #define SPINOR_OP_BE_4K_PMC 0xd7 // Erase 4KiB block on PMC chips
> #define SPINOR_OP_BE_32K 0x52 // Erase 32KiB block
> #define SPINOR_OP_CHIP_ERASE 0xc7 // Erase whole flash chip
> -#define SPINOR_OP_SE 0xd8 // Sector erase (usually 64KiB)
> +#define SPINOR_OP_BE 0xd8 // Block erase (usually 64KiB)
> #define SPINOR_OP_RDID 0x9f // Read JEDEC ID
> #define SPINOR_OP_RDSFDP 0x5a // Read SFDP
> #define SPINOR_OP_RDCR 0x35 // Read configuration register
> @@ -329,7 +329,7 @@ NorFlashReadID (
> #define SPINOR_OP_PP_1_4_4_4B 0x3e // Quad page program
> #define SPINOR_OP_BE_4K_4B 0x21 // Erase 4KiB block
> #define SPINOR_OP_BE_32K_4B 0x5c // Erase 32KiB block
> -#define SPINOR_OP_SE_4B 0xdc // Sector erase (usually 64KiB)
> +#define SPINOR_OP_BE_4B 0xdc // Block erase (usually 64KiB)
> #define SPINOR_OP_RD_ARRAY 0xe8 // Read array
> #define SPINOR_OP_RD_NVCFG 0xb5 // Read non-volatile config
> register
> #define SPINOR_OP_RD_VCR 0x85 // Read VCR register
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> index 8cdaa0eeb83f..b2ca0033ac13 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> @@ -51,12 +51,10 @@ STATIC CONST CSDC_DEFINITION mN25qCSDCDefTable[] = {
> { SPINOR_OP_READ_4B, TRUE, TRUE, FALSE, FALSE, CS_CFG_MBM_SINGLE,
> CSDC_TRP_SINGLE },
> // Write Operations
> - { SPINOR_OP_PP, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE,
> - CSDC_TRP_SINGLE },
> - { SPINOR_OP_PP_1_1_4, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_QUAD,
> + { SPINOR_OP_PP_4B, TRUE, TRUE, FALSE, TRUE, CS_CFG_MBM_SINGLE,
> CSDC_TRP_SINGLE },
> // Erase Operations
> - { SPINOR_OP_SE, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE,
> + { SPINOR_OP_BE_4B, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE,
> CSDC_TRP_SINGLE },
> };
>
> @@ -446,9 +444,8 @@ NorFlashEraseSingleBlock (
> BlockAddress -= Instance->RegionBaseAddress;
> BlockAddress += Instance->OffsetLba * Instance->BlockSize;
>
> - NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> - MmioWrite32 (Instance->DeviceBaseAddress,
> - SwapBytes32 (BlockAddress & 0x00FFFFFF) | SPINOR_OP_SE);
> + NorFlashSetHostCommand (Instance, SPINOR_OP_BE_4B);
> + MmioWrite32 (Instance->DeviceBaseAddress, SwapBytes32 (BlockAddress));
> NorFlashWaitProgramErase (Instance);
> NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
>
> @@ -515,7 +512,7 @@ NorFlashWriteSingleWord (
> if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
> return EFI_DEVICE_ERROR;
> }
> - NorFlashSetHostCommand (Instance, SPINOR_OP_PP);
> + NorFlashSetHostCommand (Instance, SPINOR_OP_PP_4B);
> MmioWrite32 (WordAddress, WriteData);
> NorFlashWaitProgramErase (Instance);
Ping. If you could take a look, it would be much appreciated.
Thanks,
Masahisa Kojima
>
> --
> 2.17.1
>
>
>
>
>
>
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