REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong <eric.d...@intel.com> Cc: Ray Ni <ray...@intel.com> Cc: Rahul Kumar <rahul1.ku...@intel.com> Signed-off-by: Sunil V L <suni...@ventanamicro.com> --- UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml index bbdc44a45b34..ae963e94c8e6 100644 --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml @@ -19,6 +19,7 @@ ], ## Both file path and directory path are accepted. "IgnoreFiles": [ + "Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h" ] }, "CompilerPlugin": { -- 2.38.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95248): https://edk2.groups.io/g/devel/message/95248 Mute This Topic: https://groups.io/mt/94330877/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-