REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V register names do not follow the EDK2 formatting.
So, add it to ignore list for now.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Acked-by: Abner Chang <abner.ch...@amd.com>
---
UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml
index a377366798b0..953361ba0479 100644
--- a/UefiCpuPkg/UefiCpuPkg.ci.yaml
+++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml
@@ -27,6 +27,7 @@
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
+ "Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h"
]
},
"CompilerPlugin": {
--
2.38.0
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