The DSA device tree binding requires setting the
CPU port mode explicitly and it was missing in the CN913x CEx7
Evaluation Board swtich description. Fix that.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
index 50e6d69..d42911c 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
@@ -285,6 +285,11 @@
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth2>;
+ phy-mode = "2500base-x";
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
};
};
--
2.29.0
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