From: Tinh Nguyen <tinhngu...@os.amperecomputing.com>
Since the commit 103fa647d159e3d76be2634d2653c2d215dd0d46 instead
("ArmPkg: Replace CoreId and ClusterId with Mpidr in ARM_CORE_INFO
struct") has updated the ARM_CORE_INFO structure so the MPIDR is now a
single field instead of separate cluster/core fields. This patch
updates the ArmPlatformLib to work with the changed ARM_CORE_INFO.
Signed-off-by: Nhi Pham <n...@os.amperecomputing.com>
---
.../Ampere/AmpereAltraPkg/Include/Platform/Ac01.h | 11 ++++++++++-
.../JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c | 5 ++---
.../JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c | 14 ++++++++------
.../Library/ArmPlatformLib/ArmPlatformLib.c | 8 +++++---
4 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
index d45688f88401..563dd5ef242d 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -229,6 +229,15 @@
//
#define PLATFORM_CPM_UID_BIT_OFFSET 8
+//
+// MPIDR manipulation
+//
+#define AC01_GET_MPIDR(SocketId, ClusterId, CoreId) \
+ (((SocketId) << 32) | ((ClusterId) << 16) | ((CoreId) << 8))
+#define AC01_GET_SOCKET_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF3) >> 32)
+#define AC01_GET_CLUSTER_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF2) >> 16)
+#define AC01_GET_CORE_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF1) >> 8)
+
//
// Max number for AC01 PCIE Root Complexes
//
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c
b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c
index 419ce578e452..4db1f9a383a9 100644
--- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -160,8 +160,7 @@ AcpiInstallMadtProcessorNode (
(ClusterId << 8) + (CpuId % PLATFORM_CPU_NUM_CORES_PER_CPM);
MadtProcessorEntryPointer->Flags = 1;
MadtProcessorEntryPointer->MPIDR =
- (((ClusterId << 8) + (CpuId % PLATFORM_CPU_NUM_CORES_PER_CPM)) << 8);
- MadtProcessorEntryPointer->MPIDR += (((UINT64)SocketId) << 32);
+ AC01_GET_MPIDR ((UINT64)SocketId, ClusterId, CpuId %
PLATFORM_CPU_NUM_CORES_PER_CPM);
return Size;
}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
index f4df60bc2593..3a89014f41f1 100644
--- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
Copyright (c) 2022, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -122,7 +122,6 @@ SratAddGiccAffinity (
UINTN Count, NumNode, Idx;
UINT32 AcpiProcessorUid;
UINT8 Socket;
- UINT8 Core;
UINT8 Cpm;
Hob = GetFirstGuidHob (&gArmMpCoreInfoGuid);
@@ -141,14 +140,17 @@ SratAddGiccAffinity (
NumNode = 0;
while (Count != NumberOfEntries) {
for (Idx = 0; Idx < NumberOfEntries; Idx++ ) {
- Socket = GET_MPIDR_AFF1 (ArmCoreInfoTable[Idx].Mpidr);
- Core = GET_MPIDR_AFF0 (ArmCoreInfoTable[Idx].Mpidr);
- Cpm = Core >> PLATFORM_CPM_UID_BIT_OFFSET;
+ Socket = AC01_GET_SOCKET_ID (ArmCoreInfoTable[Idx].Mpidr);
+ Cpm = AC01_GET_CLUSTER_ID (ArmCoreInfoTable[Idx].Mpidr);
if (CpuGetSubNumNode (Socket, Cpm) != NumNode) {
/* We add nodes based on ProximityDomain order */
continue;
}
- AcpiProcessorUid = (Socket << PLATFORM_SOCKET_UID_BIT_OFFSET) + Core;
+
+ AcpiProcessorUid =
+ (AC01_GET_SOCKET_ID (ArmCoreInfoTable[Idx].Mpidr) <<
PLATFORM_SOCKET_UID_BIT_OFFSET)
+ + (AC01_GET_CLUSTER_ID (ArmCoreInfoTable[Idx].Mpidr) <<
PLATFORM_CPM_UID_BIT_OFFSET)
+ + AC01_GET_CORE_ID (ArmCoreInfoTable[Idx].Mpidr);
ZeroMem ((VOID *)&SratGiccAffinity[Count], sizeof
(SratGiccAffinity[Count]));
SratGiccAffinity[Count].AcpiProcessorUid = AcpiProcessorUid;
SratGiccAffinity[Count].Flags = 1;
diff --git
a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c
b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index f2ec923d6f8d..18023df92880 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -108,8 +108,10 @@ PrePeiCoreGetMpCoreInfo (
}
SocketId = SOCKET_ID (Index);
ClusterId = CLUSTER_ID (Index);
- mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].Mpidr = GET_MPID (
- SocketId, (ClusterId << 8) | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM));
+
+ mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].Mpidr =
+ AC01_GET_MPIDR ((UINT64)SocketId, ClusterId, (Index %
PLATFORM_CPU_NUM_CORES_PER_CPM));
+
mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearAddress = 0;
mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearValue = 0;
mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxGetAddress = 0;
--
2.25.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#98435): https://edk2.groups.io/g/devel/message/98435
Mute This Topic: https://groups.io/mt/96240088/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
