On Fri, Jan 13, 2023 at 10:18:59AM +0000, Wu, Jiaxin wrote: > Thanks Comments Gerd, I will resolve the CI check issue (I have noticed that > in https://github.com/tianocore/edk2/pull/3884) & refine the usage > description in next version. > > Anyway, Ray also helped explain the usage as below, I will integrate it in > the hob definition .h file, help below can help understand the design.: > > The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU > runs the > SMI handler at SMBASE+0x8000. Also, the SMM save state area is within > SMBASE+0x10000. > > One of the SMM initialization from CPU perspective is to program the new > SMBASE (in TSEG range) > for each CPU thread. When the SMBASE update happens in a PEI module, the PEI > module shall > produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm > driver which runs > at a later phase about the new SMBASE for each CPU thread.
There are no PEI module changes in this patch series. So where does the HOB come from? And what are the reasons for setting SMBASE in a PEI module instead of PiSmmCpuDxeSmm? take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98476): https://edk2.groups.io/g/devel/message/98476 Mute This Topic: https://groups.io/mt/96241699/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
