From: Aryeh Chen <aryeh.c...@intel.com>
Since AlderLake platform client project align Server project to use
PC00.
Signed-off-by: Aryeh Chen <aryeh.c...@intel.com>
Cc: Chasel Chiu <chasel.c...@intel.com>,
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>,
Cc: Isaac Oram <isaac.w.o...@intel.com>,
Cc: Liming Gao <gaolim...@byosoft.com.cn>,
Cc: Eric Dong <eric.d...@intel.com>
---
Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
b/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
index 4efb8709ac..d84393d465 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
+++ b/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
@@ -23,7 +23,7 @@ DefinitionBlock (
//---------------------------------------------------------------------------
// Begin PCI tree object scope
//---------------------------------------------------------------------------
- Device(PCI0) { // PCI Bridge "Host Bridge"
+ Device(PC00) { // PCI Bridge "Host Bridge"
Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host
hierarchy
Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't
understand the new HID
Name(_SEG, 0)
--
2.26.2.windows.1
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