Current implementation for cache management (instruction/data flush/invd) depends on ifence instruction. All RV platforms may not use the same method for cache management. Instead RV defines CMO Cache management operations specification which consits of cbo.x instructions for cache management. However it requires GCC12+ to enable the same. Need to decide how cbo based implementation coexists with ifence based implementation with GCC version dependency.
This patchset is primarily to review the same and decide path forward. review branch: https://github.com/rivosinc/edk2/tree/dev_rv_cmo_v1 Dhaval Sharma (2): MdePkg/BaseCacheMaintenanceLib: Enable RISCV CMO OvmfPkg/RiscVVirt: Enable CMO support OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 9 ++ MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 126 ++++++++++++++++++-- MdePkg/Library/BaseLib/RiscV64/RiscVCpuCache.S | 23 ++++ 4 files changed, 152 insertions(+), 7 deletions(-) create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuCache.S -- 2.40.0.rc0.57.g454dfcbddf -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101795): https://edk2.groups.io/g/devel/message/101795 Mute This Topic: https://groups.io/mt/97826395/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
