On Thu, Apr 20, 2023 at 21:45:32 +0200, Marcin Juszkiewicz wrote:
> ArmCpuInfo needs to be able to read ID_AA64ISAR2_EL1 system register.
> Older toolchains do not know it.
>
> Same solution as one for QEMU:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg929586.html
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
Thanks!
Reviewed-by: Leif Lindholm <quic_llind...@quicinc.com>
I will never stop being surprised by ARM not declaring these as RAZ
and existing ahead of time. So we keep ending up with this race
condition (preventing CI on the arch feature app to pass).
/
Leif
> ---
> ArmPkg/Include/Chipset/AArch64.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/ArmPkg/Include/Chipset/AArch64.h
> b/ArmPkg/Include/Chipset/AArch64.h
> index bfd2859f5131..690433f68ec8 100644
> --- a/ArmPkg/Include/Chipset/AArch64.h
> +++ b/ArmPkg/Include/Chipset/AArch64.h
> @@ -112,6 +112,10 @@
> #define ARM_VECTOR_LOW_A32_FIQ 0x700
> #define ARM_VECTOR_LOW_A32_SERR 0x780
>
> +// The ID_AA64ISAR2_EL1 register is not recognized by older
> +// assemblers, we need to define it here.
> +#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
> +
> // The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
> // build for ARMv8.0, we need to define the register here.
> #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
> --
> 2.40.0
>
>
>
>
>
>
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