For arch X64, system will enable the page table in SPI to cover 0-512G range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting. Existing code doesn't cover the higher address access above 512G before memory-discovered callback. This series patches provide the solution to enable paging from temporary RAM Done.
Jiaxin Wu (5): UefiCpuPkg/SecCore: Migrate page table to permanent memory UefiCpuPkg/CpuMpPei: Enable PAE page table if CR0.PG is not set MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. OvmfPkg: Add CpuPageTableLib required by SecCore & CpuMpPei UefiPayloadPkg: Add CpuPageTableLib required by SecCore & CpuMpPei MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 ++-- OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/IntelTdx/IntelTdxX64.dsc | 3 +- OvmfPkg/Microvm/MicrovmX64.dsc | 2 +- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 2 +- OvmfPkg/OvmfPkgX64.dsc | 3 +- OvmfPkg/OvmfXen.dsc | 2 +- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 + UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 1 + UefiCpuPkg/CpuMpPei/CpuPaging.c | 215 +++++++++-------------- UefiCpuPkg/SecCore/SecCore.inf | 1 + UefiCpuPkg/SecCore/SecCoreNative.inf | 1 + UefiCpuPkg/SecCore/SecMain.c | 152 ++++++++++++++++ UefiCpuPkg/SecCore/SecMain.h | 4 + UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +- 17 files changed, 282 insertions(+), 151 deletions(-) -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104758): https://edk2.groups.io/g/devel/message/104758 Mute This Topic: https://groups.io/mt/98843217/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-