Adds the following header files:
* SystemAgent/Include
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Isaac Oram <isaac.w.o...@intel.com>
Cc: Rosen Chuang <rosen.chu...@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbe...@intel.com>
---
.../Include/ConfigBlock/MemoryDxeConfig.h | 126 ++++++++++
.../ConfigBlock/SaMiscPeiPreMemConfig.h | 112 +++++++++
.../Include/Library/DxeSaPolicyLib.h | 58 +++++
.../Include/Library/PeiSaPolicyLib.h | 13 ++
.../SystemAgent/Include/MemInfoHob.h | 220 ++++++++++++++++++
.../SystemAgent/Include/Protocol/SaPolicy.h | 54 +++++
.../SystemAgent/Include/SaDataHob.h | 28 +++
7 files changed, 611 insertions(+)
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
create mode 100644
Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/SaDataHob.h
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
new file mode 100644
index 0000000000..eca0c2f1ba
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDxeConfig.h
@@ -0,0 +1,126 @@
+/** @file
+ Memory DXE Policy definitions
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_DXE_CONFIG_H_
+#define _MEMORY_DXE_CONFIG_H_
+
+#pragma pack(push, 1)
+
+/**
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+ <b>Revision 1</b>: - Initial version.
+**/
+#define MEMORY_DXE_CONFIG_REVISION 2
+
+typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG;
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] Controller Desired Controller to get a
DeviceLocator string for.
+ @param[in] Dimm Desired DIMM to get a
DeviceLocator string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The DeviceLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(
+ IN CONST MEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator
field.
+ Implementation of this function is optional, if this function pointer is
NULL then
+ the reference implementation of DeviceLocator will be used.
+
+ @param[in] This A pointer to this instance of
MEMORY_DXE_CONFIG.
+ @param[in] Controller Desired Controller to get a
BankLocator string for.
+ @param[in] Dimm Desired DIMM to get a BankLocator
string for.
+ @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
+
+ @retval The BankLocator string
+ @retval NULL If the return value is NULL, the
default value will be used.
+**/
+typedef
+CHAR8*
+(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(
+ IN CONST MEMORY_DXE_CONFIG *This,
+ IN UINT8 Controller,
+ IN UINT8 Dimm,
+ IN UINT8 MdSocket
+ );
+
+/**
+ The Memory Configuration includes DIMM SPD address Map and DIMM Slot
Mechanical present bit map.
+ The data elements should be initialized by a Platform Module.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+struct _MEMORY_DXE_CONFIG {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config
Block Header
+/**
+ Offset 28:
+ Dimm SPD address
+ Only Server support 2 channels * 3 slots per channel = 6 sockets totally
+ The Desktop and mobile only support 2 channels * 2 slots per channel = 4
sockets totally
+ So there is mapping rule here for Desktop and mobile that there are no more
4 DIMMS totally in a system:
+ Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0]
+ Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1]
+ Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2]
+ Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3]
+ Refer to SmbiosMemory.c for use
+ If change the mapping rule, please update the Revision number.
+**/
+ UINT8 *SpdAddressTable;
+/**
+ Offset 36:
+ ChannelASlotMap and ChannelBSlotMap change to use SlotMap as the DIMM slot
map solution.
+ Reserve 2-bytes in order to comply with 4-bytes alignment and keep the
offset of other members.
+**/
+ UINT8 ChannelASlotMap;
+ UINT8 ChannelBSlotMap;
+/**
+ Offset 38:
+ MRC execution time measurement: <b>0=Disable</b>, 1=Enable
+**/
+ UINT8 MrcTimeMeasure;
+/**
+ Offset 39:
+ Fast boot: 0=Disable, <b>1=Enable</b>
+**/
+ UINT8 MrcFastBoot;
+/**
+ Offset 40:
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator
field.
+**/
+ MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING GetDeviceLocatorString;
+/**
+ Offset 48:
+ Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator
field.
+**/
+ MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING GetBankLocatorString;
+/**
+ Offset 56:
+ Each DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1,
...
+ if the bit is 1, the related DIMM slot is present.
+ E.g. if memory controller 0 channel 3 has 2 DIMMs, SlotMap[0][3] = 0x03;
+ E.g. if memory controller 1 channel 2 has only 1 DIMMs, SlotMap[1][2] = 0x0;
+**/
+ UINT8 **SlotMap;
+};
+#pragma pack(pop)
+
+#endif // _MEMORY_DXE_CONFIG_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
new file mode 100644
index 0000000000..cb75696b61
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h
@@ -0,0 +1,112 @@
+/** @file
+ Policy details for miscellaneous configuration in System Agent
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_
+#define _SA_MISC_PEI_PREMEM_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#ifndef MEM_CFG_MAX_SOCKETS
+#define MEM_CFG_MAX_SOCKETS 16
+#endif
+
+#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 1
+
+/**
+ This configuration block is to configure SA Miscellaneous variables during
PEI Pre-Mem phase like programming
+ different System Agent BARs, TsegSize, MmioSize required etc.
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
Header
+ /**
+ Offset 28 Memory DIMMs' SPD address for reading SPD data.
+ TGL Mapping
+ 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
+ 1 - Controller 0 Channel 0 Dimm 1 - DDR4
+ 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
+ 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC
+ 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
+ 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
+ 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
+ 9 - Controller 1 Channel 0 Dimm 1 - DDR4
+ 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
+ 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC
+ 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
+ 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
+ **/
+ UINT8 SpdAddressTable[MEM_CFG_MAX_SOCKETS];
+ VOID *S3DataPtr; ///< Offset 44 Memory data save
pointer for S3 resume. The memory space should be allocated and filled with
proper S3 resume data on a resume path
+ UINT32 SmbusBar; ///< Offset 48 Address of System
Agent SMBUS BAR: <b>0xEFA0</b>
+ /**
+ Offset 52 Size of TSEG in bytes. (Must be power of 2)
+ <b>0x400000</b>: 4MB for Release build (When IED enabled, it will be 8MB)
+ 0x1000000 : 16MB for Debug build (Regardless IED enabled or disabled)
+ **/
+ UINT32 TsegSize;
+ /**
+ Offset 56
+ <b>(Test)</b> Size of IED region in bytes.
+ <b>0</b> : IED Disabled (no memory occupied)
+ 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG)
+ <b>Note: Enabling IED may also enlarge TsegSize together.</b>
+ @deprecated
+ **/
+ UINT32 IedSize;
+ UINT32 SkipExtGfxScan:1; ///< <b>(Test)</b> OFfset 60:0
:1=Skip External Gfx Device Scan; <b>0=Scan for external graphics devices</b>.
Set this policy to skip External Graphics card scanning if the platform uses
Internal Graphics only.
+ UINT32 BdatEnable:1; ///< Offset 60:1 :This field
enables the generation of the BIOS DATA ACPI Tables: <b>0=FALSE</b>, 1=TRUE.
+ UINT32 TxtImplemented:1; ///< OFfset 60:2 :This field
currently is used to tell MRC if it should run after TXT initializatoin
completed: <b>0=Run without waiting for TXT</b>, 1=Run after TXT initialization
by callback
+ /**
+ Offset 60:3 :
+ <b>(Test)</b> Scan External Discrete Graphics Devices for Legacy Only VGA
OpROMs
+
+ When enabled, if the primary graphics device is an external discrete
graphics device, Si will scan the
+ graphics device for legacy only VGA OpROMs.
+
+ This is intended to ease the implementation of a BIOS feature to
automatically enable CSM if the Primary Gfx device
+ only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM
won't result in no video being displayed.
+ This is useful for platforms that implement PCIe slots that allow the end
user to install an arbitrary Gfx device.
+
+ This setting will only take effect if SkipExtGfxScan == 0. It is ignored
otherwise.
+
+ - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
+ - <b>Enabled</b> (0x1) : Scan External Gfx for Legacy Only VGA OpROM
+ **/
+ UINT32 ScanExtGfxForLegacyOpRom:1;
+ UINT32 RsvdBits0 :28; ///< Offset 60:4 :Reserved for
future use
+ UINT8 UserBd; ///< Offset 64 <b>0=Mobile/Mobile
Halo</b>, 1=Desktop/DT Halo, 2=Desktop 2DPC DDR5, 5=ULT/ULX/Mobile Halo Type3,
6=ULT/ULX/Mobile Halo Type4, 8=UP Server
+ UINT8 LockPTMregs; ///< <b>(Test)</b> Offset 65 Lock
PCU Thermal Management registers: 0=FALSE, <b>1=TRUE</b>
+ UINT8 BdatTestType; ///< Offset 66 When BdatEnable is
set to TRUE, this option selects the type of data which will be populated in
the BIOS Data ACPI Tables: <b>0=RMT</b>, 1=RMT Per Bit, 2=Margin 2D.
+ UINT8 CridEnable; ///< Offset 67 For Platforms
supporting Intel(R) SIPP, this policy is use control enable/disable
Compatibility Revision ID (CRID) feature: <b>0=FALSE</b>, 1=TRUE
+ UINT32 AcpiReservedMemorySize; ///< Offset 68 The Size of a
Reserved memory buffer allocated in previous boot for S3 resume used.
Originally it is retrieved from AcpiVariableCompatibility variable.
+ UINT64 AcpiReservedMemoryBase; ///< Offset 80 The Base address
of a Reserved memory buffer allocated in previous boot for S3 resume used.
Originally it is retrieved from AcpiVariableCompatibility variable.
+ UINT64 SystemMemoryLength; ///< Offset 88 Total system
memory length from previous boot, this is required for S3 resume. Originally it
is retrieved from AcpiVariableCompatibility variable.
+
+ UINT8 WrcFeatureEnable; ///< Offset 96: Enable/Disable
WRC (Write Cache) feature of IOP. When enabled, supports IO devices allocating
onto the ring and into LLC.
+ UINT8 FirstDimmBitMask; ///< Offset 97: Defines which
DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask:
Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the
first DIMM to be populated should be set to '1'.
+ ///< Note: this mask
is only for non-ECC DIMM.
+ UINT8 FirstDimmBitMaskEcc; ///< Offset 98: Defines which
ECC DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask:
Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the
first DIMM to be populated should be set to '1'.
+ ///< For example, if
one MC is T-topology, there is no special population rule, can put it as 11 for
this MC and it means either D0 or D1 can be
+ ///< be populated
firstly.
+ ///< Note: this mask
is only for ECC DIMM, not for non-ECC DIMM.
+
+ UINT8 DisableMrcRetrainingOnRtcPowerLoss; ///< Offset 99: Enable/Disable
DisableMrcRetrainingOnRtcPowerLoss.
+
+
+ // Since the biggest element is UINT64, this structure should be aligned
with 64 bits.
+ UINT8 Rsvd[4]; ///< Reserved for config block
alignment.
+ UINT8 ResizableBarSupport;
+
+ UINT8 Rsrvd1[7];
+} SA_MISC_PEI_PREMEM_CONFIG;
+#pragma pack(pop)
+
+#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h
new file mode 100644
index 0000000000..5f5eeeeb63
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h
@@ -0,0 +1,58 @@
+/** @file
+ Prototype of the DxeSaPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_SA_POLICY_LIB_H_
+#define _DXE_SA_POLICY_LIB_H_
+
+#include <Protocol/SaPolicy.h>
+
+/**
+ This function prints the DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol
+**/
+VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+;
+
+/**
+ CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SaPolicy The pointer to get SA Policy Protocol
instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks(
+ IN OUT SA_POLICY_PROTOCOL **SaPolicy
+);
+
+/**
+ SaInstallPolicyProtocol installs SA Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please
update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SaPolicy The pointer to SA Policy Protocol
instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+;
+
+#endif // _DXE_SA_POLICY_LIB_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h
new file mode 100644
index 0000000000..8b941b4420
--- /dev/null
+++
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h
@@ -0,0 +1,13 @@
+/** @file
+ Prototype of the PeiSaPolicy library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_SA_POLICY_LIB_H_
+#define _PEI_SA_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+#endif // _PEI_SA_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
new file mode 100644
index 0000000000..d6c670d4ce
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
@@ -0,0 +1,220 @@
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE 2
+#define MAX_CH 4
+#define MAX_DIMM 2
+#define HOB_MAX_SAGV_POINTS 4
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the
controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is
disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is
enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be
detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of
presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair
and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR5
+#define MRC_DDR_TYPE_DDR5 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR5
+#define MRC_DDR_TYPE_LPDDR5 2
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4 3
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 4
+#endif
+
+#define MAX_PROFILE_NUM 7 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command
rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS
latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum
CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum
four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum
active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum
RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum
Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum
refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum
per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum
refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum
refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum
row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum
row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum
row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum
row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum
internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum
write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum
internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum
internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum
internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum
CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+typedef struct {
+ UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
+} MRC_IP_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the
definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3
is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this
DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType
information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType
information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth
information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing
information needed for SMBIOS structure creation.
+ UINT16 Speed; ///< The maximum capable speed of
the device, in MHz
+ UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1
= Socketed. Needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this
channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that
exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output
characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this
controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this
memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this
memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that
exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel
level definitions.
+} CONTROLLER_INFO;
+
+/// This data structure contains per-SaGv timing values that are considered
output by the MRC.
+typedef struct {
+ UINT32 DataRate; ///< The memory rate for the current SaGv Point
in units of MT/s
+ MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding
SaGv Point - derived from JEDEC SPD spec
+ MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding
SaGv Point - IP specific
+} HOB_SAGV_TIMING_OUT;
+
+/// This data structure contains SAGV config values that are considered output
by the MRC.
+typedef struct {
+ UINT32 NumSaGvPointsEnabled; ///< Count of the total number of
SAGV Points enabled.
+ UINT32 SaGvPointMask; ///< Bit mask where each bit
indicates an enabled SAGV point.
+ HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
+} HOB_SAGV_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this
memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or
LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of
the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock
speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT8 IsDMBRunning; ///< Deprecated.
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK
value read from SPD XMP profiles if they exist.
+ ///
+ /// Set of bit flags showing XMP and User Profile capability status for the
DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
+ /// Bit 0: XMP Profile 1 capability status
+ /// Bit 1: XMP Profile 2 capability status
+ /// Bit 2: XMP Profile 3 capability status
+ /// Bit 3: User Profile 4 capability status
+ /// Bit 4: User Profile 5 capability status
+ ///
+ UINT8 XmpProfileEnable;
+ UINT8 XmpConfigWarning; ///< If XMP capable
DIMMs config support only 1DPC, but 2DPC is installed
+ UINT8 Ratio; ///< DDR Frequency
Ratio, Max Value 255
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ UINT32 VddqVoltage[MAX_PROFILE_NUM];
+ UINT32 VppVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+ UINT16 Ratio_UINT16; ///< DDR Frequency
Ratio, used for programs that require ratios higher then 255
+ UINT32 NumPopulatedChannels; ///< Total number of
memory channels populated
+ HOB_SAGV_INFO SagvConfigInfo; ///< This data
structure contains SAGV config values that are considered output by the MRC.
+ UINT16 TotalMemWidth; ///< Total Memory Width
in bits from all populated channels
+ BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM
BIOS to display a warning on the screen that DDR speed was reduced due to wrong
DIMM population
+ BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM
BIOS to display a warning on the screen that DDR speed was reduced due to mixed
DIMM config
+ BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic
Memory Boost failed to train and was force disabled on the last full training
boot. FALSE otherwise.
+} MEMORY_INFO_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
diff --git
a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
new file mode 100644
index 0000000000..cc258debe1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
@@ -0,0 +1,54 @@
+/** @file
+ Interface definition details between System Agent and platform drivers
during DXE phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_POLICY_H_
+#define _SA_POLICY_H_
+
+#include <ConfigBlock.h>
+#include <Library/ConfigBlockLib.h>
+#include <GraphicsConfig.h>
+#include <ConfigBlock/MemoryDxeConfig.h>
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gSaPolicyProtocolGuid;
+extern EFI_GUID gGraphicsDxeConfigGuid;
+extern EFI_GUID gMemoryDxeConfigGuid;
+
+/**
+ Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external
+ modules maybe have consumed this macro in their source code. Directly
+ update the SA_POLICY_PROTOCOL_REVISION version number may cause those
+ external modules to auto mark themselves wrong version info.
+ Always create new version macro for new Policy protocol interface.
+**/
+#define SA_POLICY_PROTOCOL_REVISION 1
+
+
+
+
+/**
+ SA DXE Policy
+
+ The SA_POLICY_PROTOCOL producer drvier is recommended to
+ set all the SA_POLICY_PROTOCOL size buffer zero before init any member
parameter,
+ this clear step can make sure no random value for those unknow new version
parameters.
+
+ Make sure to update the Revision if any change to the protocol, including the
existing
+ internal structure definations.\n
+ Note: Here revision will be bumped up when adding/removing any config block
under this structure.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31
+/*
+ Individual Config Block Structures are added here in memory as part of
AddConfigBlock()
+*/
+} SA_POLICY_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/SaDataHob.h
b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/SaDataHob.h
new file mode 100644
index 0000000000..bded1851f4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Include/SaDataHob.h
@@ -0,0 +1,28 @@
+/** @file
+ The GUID definition for SaDataHob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_DATA_HOB_H_
+#define _SA_DATA_HOB_H_
+
+#include <Base.h>
+#include <CpuPcieInfo.h>
+#include <Library/PcdLib.h>
+
+extern EFI_GUID gSaDataHobGuid;
+#pragma pack (push,1)
+
+///
+/// System Agent Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob
type structure for gSaDataHobGuid
+ UINT8 PrimaryDisplay;
+ BOOLEAN ResizableBarSupport; ///<
Resizable BAR Support
+ UINT8 Rsvd1[2]; ///< Reserved
for future use
+} SA_DATA_HOB;
+
+#pragma pack (pop)
+#endif
--
2.36.1.windows.1
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