From: Narinder Dhillon <ndhil...@marvell.com>
New Marvell package name, path, and token space needs to be propagated
to all dependent files.
Signed-off-by: Narinder Dhillon <ndhil...@marvell.com>
---
.../Armada80x0McBin/Armada80x0McBin.dsc | 116 +++++++++---------
.../Armada80x0McBinBoardDescLib.inf | 2 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../BoardDescriptionLib.inf | 2 +-
.../Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 40 +++---
.../Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 56 ++++-----
.../Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 56 ++++-----
.../Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 60 ++++-----
.../Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 6 +-
.../NonDiscoverableInitLib.inf | 2 +-
10 files changed, 171 insertions(+), 171 deletions(-)
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
index 9196300572..469ccc7083 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -48,54 +48,54 @@
################################################################################
[PcdsFixedAtBuild.common]
#Platform description
- gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin"
- gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
+ gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 8040
MacchiatoBin"
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
#MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3
# APN806-A0 MPP SET
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,
0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x3 }
# CP110 MPP SET - master
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2,
0x2, 0x2, 0xA }
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE,
0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7,
0x2, 0x2, 0x2, 0x2, 0xA }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0,
0x0, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
# CP110 MPP SET - slave
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8,
0x8, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3,
0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF,
0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4,
0x4, 0x8, 0x8, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3,
0x3, 0x3, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0,
0xFF, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
#SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF4700680
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
#ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
# ComPhy0
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -103,8 +103,8 @@
# 3: PCIE0 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SATA1 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0),
$(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G),
$(CP_5G), $(CP_10_3125G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0),
$(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),
$(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
# ComPhy1
# 0: SGMII1 1.25 Gbps
# 1: SATA0 5 Gbps
@@ -112,36 +112,36 @@
# 3: SATA1 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SGMII2 3.125 Gbps
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2),
$(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G),
$(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1),
$(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G),
$(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
#UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0
}
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
#MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
#PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
#NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI),
$(PHY_SGMII), $(PHY_SGMII) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI),
$(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
#PciEmulation
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
#RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000
diff --git
a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
index 4ebe4c3883..3fbfd9f5c7 100644
---
a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
+++
b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
@@ -22,7 +22,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git
a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
index 469a0323ca..824e10f0b2 100644
---
a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+++
b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -30,7 +30,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git
a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
index ea13ff7ad7..00bf3ff550 100644
---
a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
+++
b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
@@ -23,7 +23,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
index ad0983087d..0b02740242 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
@@ -15,7 +15,7 @@
################################################################################
[PcdsFixedAtBuild.common]
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
# ComPhy0
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -23,32 +23,32 @@
# 3: PCIE0 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SGMII2 3.125 Gbps
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0),
$(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G),
$(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0),
$(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),
$(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1) }
# MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }
# PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_1000), $(PHY_SPEED_2500) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII),
$(PHY_SGMII) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI),
$(PHY_RGMII), $(PHY_SGMII) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
index c6b0cefa8d..e9a6e34a32 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
@@ -15,25 +15,25 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|2
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3
# CP115 #1 MPP
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3,
0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x7, 0x7 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2,
0x8, 0x8, 0x9 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3,
0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x7, 0x7 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2,
0x2, 0x2, 0x8, 0x8, 0x9 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
# ComPhy1
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -41,24 +41,24 @@
# 3: SATA1 5 Gbps
# 4: PCIE1 5 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0),
$(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),
$(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0),
$(CP_PCIE0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),
$(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1
}
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII),
$(PHY_SGMII), $(PHY_SFI) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI),
$(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
index 34f9a3f2fb..74695221c4 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
@@ -15,25 +15,25 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|3
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|4
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|4
# CP115 #2 MPP
- gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
- gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0x0, 0x7, 0x7 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0x2,
0x2, 0x8, 0x8, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0x0,
0x0, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0x0, 0x7, 0x7 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF,
0xFF, 0x2, 0x2, 0x8, 0x8, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF,
0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
# ComPhy2
# 0: PCIE0 5 Gbps
# 1: USB3_HOST0 5 Gbps
@@ -41,24 +41,24 @@
# 3: SATA1 5 Gbps
# 4: PCIE1 5 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST0),
$(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
- gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G),
$(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0),
$(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G),
$(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1,
0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0,
0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0),
$(UTMI_USB_HOST1) }
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII),
$(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0,
0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),
$(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI),
$(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF
}
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1,
0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
index 17463c09c6..31e553ee41 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
@@ -15,53 +15,53 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2
# APN807 MPP
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,
0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x3 }
# CP115 #0 MPP
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3,
0x3, 0x3, 0x3 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3,
0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x7, 0x7 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2,
0x2, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0xE,
0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3,
0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3,
0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x7, 0x7 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0,
0x2, 0x2, 0x2, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2,
0xB, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0 }
# I2C
- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 }
- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000
# SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
# RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
# Variable store
- gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000
[PcdsDynamicDefault.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xEF3C0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xEF3E0000
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
index 6cb82acb13..b995ce0ef1 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
@@ -52,6 +52,6 @@
[PcdsFixedAtBuild.common]
#Platform description
- gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Board"
- gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
+ gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation
Board"
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
diff --git
a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
index c58ba8397a..a388ecab02 100644
---
a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+++
b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -24,7 +24,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
--
2.34.1
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