On Thu, Oct 12, 2023 at 1:12 PM Sunil V L <suni...@ventanamicro.com> wrote: > > Hi Ray, > > On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote: > > Introduce a PCD to control the maximum SATP mode that MMU allowed > > to use. This PCD helps RISC-V platform set bare or minimum SATP mode > > during bring up to debug memory map issue. > > > Could you help with review of this?
It seems glaring to me that Maintainers.txt needs some sort of RISCV F: */*RiscV*/ pattern for riscv architectural changes across all packages - I'm not sure how much value the x86 Intel folks can add to RISCV or ARM code review and merging, apart from the traditional UEFI/tianocore feedback. -- Pedro -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109577): https://edk2.groups.io/g/devel/message/109577 Mute This Topic: https://groups.io/mt/101761642/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
