From: mindachen1987 <minda.c...@starfivetech.com>
Cc: Sunil V L <suni...@ventanamicro.com>
Co-authored-by: John Chew <yuinyee.c...@starfivetech.com>
Signed-off-by: mindachen1987 <minda.c...@starfivetech.com>
---
Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h | 24 +++++++++++
Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec | 45
++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h
b/Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h
new file mode 100644
index 000000000000..b6875f6aa82b
--- /dev/null
+++ b/Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h
@@ -0,0 +1,24 @@
+/** @file
+ *
+ * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef JH7110_H__
+#define JH7110_H__
+
+// #define JH7110_SOC_REGISTERS (FixedPcdGet64
(PcdJH7110RegistersAddress))
+// #define JH7110_SOC_REGISTER_LENGTH 0x02000000
+
+/* Generic PCI addresses */
+#define PCIE_TOP_OF_MEM_WIN (FixedPcdGet64 (PcdJH7110PciBusMmioAdr))
+#define PCIE_CPU_MMIO_WINDOW (FixedPcdGet64 (PcdJH7110PciCpuMmioAdr))
+#define PCIE_BRIDGE_MMIO_LEN (FixedPcdGet32 (PcdJH7110PciBusMmioLen))
+
+/* PCI root bridge control registers location */
+#define PCIE_REG_BASE (FixedPcdGet64 (PcdJH7110PciRegBase))
+#define PCIE_CONFIG_BASE (FixedPcdGet64 (PcdJH7110PciConfigRegBase))
+
+#endif /* JH7110_H__ */
diff --git a/Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec
b/Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec
new file mode 100644
index 000000000000..438557a15500
--- /dev/null
+++ b/Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec
@@ -0,0 +1,45 @@
+## @file
+#
+# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = JH7110Pkg
+ PACKAGE_GUID = D4B585C5-EBCA-4779-B974-05A3CF2F10C4
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+
+[Guids]
+ gJH7110TokenSpaceGuid = {0x44045e56, 0x7056, 0x4be6, {0x88, 0xc0, 0x49,
0x0c, 0x67, 0x90, 0x2f, 0xba}}
+
+[PcdsFixedAtBuild.common]
+# Memory map
+ gJH7110TokenSpaceGuid.PcdJH7110FlashVarOffset|0x0|UINT32|0x00000001
+
+# PCIe
+ gJH7110TokenSpaceGuid.PcdJH7110RegistersAddress|0|UINT32|0x00000002
+ gJH7110TokenSpaceGuid.PcdJH7110PciRegBase|0x2b000000|UINT64|0x00000003
+ gJH7110TokenSpaceGuid.PcdJH7110PciBusMmioAdr|0x0|UINT64|0x00000004
+ gJH7110TokenSpaceGuid.PcdJH7110PciBusMmioLen|0x0|UINT32|0x00000005
+ gJH7110TokenSpaceGuid.PcdJH7110PciCpuMmioAdr|0x0|UINT64|0x00000006
+ gJH7110TokenSpaceGuid.PcdJH7110PciConfigRegBase|0x940000000|UINT64|0x00000007
+
+# SPI
+ gJH7110TokenSpaceGuid.PcdSpiFlashRegBase|0|UINT32|0x10000008
+ gJH7110TokenSpaceGuid.PcdSpiFlashAhbBase|0|UINT64|0x10000009
+ gJH7110TokenSpaceGuid.PcdSpiFlashFifoWidth|0|UINT8|0x10000010
+ gJH7110TokenSpaceGuid.PcdSpiFlashRefClkHz|0|UINT32|0x10000011
+ gJH7110TokenSpaceGuid.PcdSpiFlashTshslNs|0|UINT32|0x10000012
+ gJH7110TokenSpaceGuid.PcdSpiFlashTsd2dNs|0|UINT32|0x1000013
+ gJH7110TokenSpaceGuid.PcdSpiFlashTchshNs|0|UINT32|0x1000014
+ gJH7110TokenSpaceGuid.PcdSpiFlashTslchNs|0|UINT32|0x1000015
+
+[Protocols]
+ gJH7110SpiMasterProtocolGuid = { 0xA33C46E0, 0x4FB6, 0x4AA3, { 0x8E, 0x66,
0x00, 0x06, 0x9F, 0x3A, 0x11, 0x81 }}
+ gJH7110SpiFlashProtocolGuid = { 0x5ECECDF6, 0x81DA, 0x4E10, { 0x9D, 0x4B,
0x26, 0x65, 0x8C, 0x03, 0xAB, 0xBC }}
--
2.34.1
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