There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity.
Cc: Michael D Kinney <michael.d.kin...@intel.com> Cc: Liming Gao <gaolim...@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang....@intel.com> Cc: Sunil V L <suni...@ventanamicro.com> Cc: Daniel Schaefer <g...@danielschaefer.me> Cc: Laszlo Ersek <ler...@redhat.com> Signed-off-by: Dhaval Sharma <dha...@rivosinc.com> Reviewed-by: Laszlo Ersek <ler...@redhat.com> --- Notes: V7: - Add RB tag V6: - As part of restructuring, adding cache instruction differentiation in function naming MdePkg/Include/Library/BaseLib.h | 4 ++-- MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++-- MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 7142bbfa42f2..d4b56a9601da 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt ( **/ VOID EFIAPI -RiscVInvalidateInstCacheAsm ( +RiscVInvalidateInstCacheAsmFence ( VOID ); @@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm ( **/ VOID EFIAPI -RiscVInvalidateDataCacheAsm ( +RiscVInvalidateDataCacheAsmFence ( VOID ); diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c index d5efcf49a4bf..4eb18edb9aa7 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -21,7 +21,7 @@ InvalidateInstructionCache ( VOID ) { - RiscVInvalidateInstCacheAsm (); + RiscVInvalidateInstCacheAsmFence (); } /** @@ -193,7 +193,7 @@ InvalidateDataCache ( VOID ) { - RiscVInvalidateDataCacheAsm (); + RiscVInvalidateDataCacheAsmFence (); } /** diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S index 7c10fdd268af..e0eea0b5fb25 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -9,13 +9,13 @@ //------------------------------------------------------------------------------ .align 3 -ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm) -ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence) +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence) -ASM_PFX(RiscVInvalidateInstCacheAsm): +ASM_PFX(RiscVInvalidateInstCacheAsmFence): fence.i ret -ASM_PFX(RiscVInvalidateDataCacheAsm): +ASM_PFX(RiscVInvalidateDataCacheAsmFence): fence ret -- 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110264): https://edk2.groups.io/g/devel/message/110264 Mute This Topic: https://groups.io/mt/102256464/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-