On Thu, Nov 09, 2023 at 10:23:02 +0100, Pierre Gondois wrote:
> To enable AARCH64 native instruction support for Openssl,
> some interfaces must be implemented. OPENSSL_cpuid_setup()
> allows to probe the supported features of the platform.
>
> Add ArmReadIdAA64Isar0Reg() to read the AA64Isar0, containing
> Arm64 instruction capabilities.
> A similar ArmReadIdAA64Isar0() function is available in the ArmPkg,
> but the CryptoPkg where OPENSSL_cpuid_setup will reside cannot rely
> on the ArmPkg.
The word "similar" here does an exemplary job of explaining why this
is problematic.
/
Leif
> Signed-off-by: Pierre Gondois <pierre.gond...@arm.com>
> ---
> MdePkg/Include/Library/BaseLib.h | 72 +++++++++++++++++++
> .../BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S | 30 ++++++++
> .../BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm | 30 ++++++++
> MdePkg/Library/BaseLib/BaseLib.inf | 2 +
> 4 files changed, 134 insertions(+)
> create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S
> create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm
>
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index b81c9dd83508..365d50cfb1b8 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -140,6 +140,78 @@ ArmReadCntPctReg (
> VOID
> );
>
> +//
> +// Bit shifts for the ID_AA64ISAR0_EL1 register.
> +//
> +#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)
> +#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)
> +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)
> +#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)
> +#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)
> +#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)
> +#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)
> +#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)
> +#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)
> +#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)
> +
> +//
> +// Bit masks for the ID_AA64ISAR0_EL1 fields.
> +//
> +#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)
> +
> +//
> +// Bit masks for the ID_AA64ISAR0_EL1 field values.
> +//
> +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)
> +
> +/**
> + Reads the current value of ID_AA64ISAR0_EL1 register.
> +
> + Reads and returns the current value of ID_AA64ISAR0_EL1.
> + This function is only available on AARCH64.
> +
> + @return The current value of ID_AA64ISAR0_EL1
> +**/
> +UINT64
> +EFIAPI
> +ArmReadIdAA64Isar0Reg (
> + VOID
> + );
> +
> #endif // defined (MDE_CPU_AARCH64)
>
> #if defined (MDE_CPU_RISCV64)
> diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S
> b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S
> new file mode 100644
> index 000000000000..4e61b869a401
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S
> @@ -0,0 +1,30 @@
> +#------------------------------------------------------------------------------
> +#
> +# ArmReadIdAA64Isar0Reg() for AArch64
> +#
> +# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#------------------------------------------------------------------------------
> +
> +.text
> +.p2align 2
> +GCC_ASM_EXPORT(ArmReadIdAA64Isar0Reg)
> +
> +#/**
> +# Reads the ID_AA64ISAR0 Register.
> +#
> +# @return The contents of the ID_AA64ISAR0 register.
> +#
> +#**/
> +#UINT64
> +#EFIAPI
> +#ArmReadIdAA64Isar0Reg (
> +# VOID
> +# );
> +#
> +ASM_PFX(ArmReadIdAA64Isar0Reg):
> + AARCH64_BTI(c)
> + mrs x0, id_aa64isar0_el1
> + ret
> diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm
> b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm
> new file mode 100644
> index 000000000000..790fb905d001
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm
> @@ -0,0 +1,30 @@
> +;------------------------------------------------------------------------------
> +;
> +; ArmReadIdAA64Isar0Reg() for AArch64
> +;
> +; Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
> +;
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +;------------------------------------------------------------------------------
> +
> + EXPORT ArmReadIdAA64Isar0Reg
> + AREA BaseLib_LowLevel, CODE, READONLY
> +
> +;/**
> +; Reads the ID_AA64ISAR0 Register.
> +;
> +; @return The contents of the ID_AA64ISAR0 register.
> +;
> +;**/
> +;UINT64
> +;EFIAPI
> +;ArmReadIdAA64Isar0Reg (
> +; VOID
> +; );
> +;
> +ArmReadIdAA64Isar0Reg
> + mrs x0, id_aa64isar0_el1
> + ret
> +
> + END
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 24e5e6c3ecb5..299bcaa56d39 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -377,6 +377,7 @@ [Sources.AARCH64]
> AArch64/CpuBreakpoint.S | GCC
> AArch64/SpeculationBarrier.S | GCC
> AArch64/ArmReadCntPctReg.S | GCC
> + AArch64/ArmReadIdAA64Isar0Reg.S | GCC
>
> AArch64/MemoryFence.asm | MSFT
> AArch64/SwitchStack.asm | MSFT
> @@ -387,6 +388,7 @@ [Sources.AARCH64]
> AArch64/CpuBreakpoint.asm | MSFT
> AArch64/SpeculationBarrier.asm | MSFT
> AArch64/ArmReadCntPctReg.asm | MSFT
> + AArch64/ArmReadIdAA64Isar0Reg.asm | MSFT
>
> [Sources.RISCV64]
> Math64.c
> --
> 2.25.1
>
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