Hi Ard, I take it this means that the IP can be synthesized in both little and big endian versions, right?
Yes, correct. Is there no ID register in the hardware you can derive this information from? Yes, in RISC-V we can determine the CPU endianness based on mstatus.MBE and mstatus.SBE register in M-Mode and S-Mode respectively. However, this driver will be used for other architecture, so reading this register will not make sense for other architectures such as ARM and x86. I have not seen any API to call in EDK2 in order to check for CPU endiness. Alternatively, I can update the handling by using software checking for the CPU endianness as follows: This will not use PCD to determine the CPU endianness. I will change this handling in the coming patch series if you think it is okay. Thank you for your time =) Regards, John -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111727): https://edk2.groups.io/g/devel/message/111727 Mute This Topic: https://groups.io/mt/102357273/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
