Hi,
> + //
> + // 4-level paging supports translating 48-bit linear addresses to 52-bit
> physical addresses.
> + // Since linear addresses are sign-extended, the linear-address space of
> 4-level paging is:
> + // [0, 2^47-1] and [0xffff8000_00000000, 0xffffffff_ffffffff].
> + // So only [0, 2^47-1] linear-address range maps to the identical
> physical-address range when
> + // 5-Level paging is disabled.
> + //
> + ASSERT (PhysicalAddressBits <= 52);
> + if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 47)) {
> + PhysicalAddressBits = 47;
> + }
Nice.
Reviewed-by: Gerd Hoffmann <[email protected]>
take care,
Gerd
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