From: Duke Zhai <duke.z...@amd.com>
BZ #:4640
Chachani board platform code depends on some AGESA-related PCDs/GUIDs.
Add AgesaPublicPkg for AGESA-related PCDs/GUIDs to support platfrom build.
Signed-off-by: Duke Zhai <duke.z...@amd.com>
Cc: Eric Xing <eric.x...@amd.com>
Cc: Ken Yao <ken....@amd.com>
Cc: Igniculus Fu <igniculus...@amd.com>
Cc: Abner Chang <abner.ch...@amd.com>
---
.../VanGoghBoard/AgesaPublic/AgesaPublic.dec | 61 +++++
.../VanGoghBoard/AgesaPublic/Include/AGESA.h | 35 +++
.../VanGoghBoard/AgesaPublic/Include/AMD.h | 189 +++++++++++++
.../AgesaPublic/Include/AmdPspDirectory.h | 55 ++++
.../AgesaPublic/Include/FchRegistersCommon.h | 23 ++
.../Include/Guid/AmdMemoryInfoHob.h | 51 ++++
.../Include/Library/AmdPspBaseLibV2.h | 248 ++++++++++++++++++
.../Include/Library/AmdPspCommonLib.h | 29 ++
.../Include/Library/AmdPspFtpmLib.h | 94 +++++++
.../AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h | 80 ++++++
.../Include/Protocol/AmdPspFtpmProtocol.h | 112 ++++++++
11 files changed, 977 insertions(+)
create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AGESA.h
create mode 100644 Platform/AMD/VanGoghBoard/AgesaPublic/Include/AMD.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/AmdPspDirectory.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/FchRegistersCommon.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Guid/AmdMemoryInfoHob.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspBaseLibV2.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspCommonLib.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspFtpmLib.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h
create mode 100644
Platform/AMD/VanGoghBoard/AgesaPublic/Include/Protocol/AmdPspFtpmProtocol.h
diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
new file mode 100644
index 0000000000..e987b9b603
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/AgesaPublic.dec
@@ -0,0 +1,61 @@
+## @file
+# EDK II AgesaPublic.dec file
+#
+# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = AgesaPublic
+ PACKAGE_GUID = EA54B0FA-908C-43DE-95A5-5E821A893CA4
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+
+[Guids]
+ gEfiAmdAgesaModulePkgTokenSpaceGuid = { 0x7788adf0, 0x9788, 0x4a3f, {
0x83, 0xfa, 0xcb, 0x51, 0x2e, 0x7c, 0xf8, 0xdd } }
+ gEfiAmdAgesaPkgTokenSpaceGuid = { 0xd4d8435f, 0xfffb, 0x4acb, {
0xa0, 0x4d, 0xff, 0x0f, 0xad, 0x67, 0x7f, 0xe9 } }
+ gAmdCpmPkgTokenSpaceGuid = { 0x916e0ddd, 0x2bd2, 0x4704, {
0x93, 0xb9, 0x59, 0x4b, 0x01, 0xa5, 0xfa, 0x9f } }
+ gAmdResourceSizeForEachRbGuid = { 0x542b8f2f, 0xbd52, 0x4233, {
0x8c, 0x3d, 0x66, 0x53, 0x0d, 0xe8, 0xa3, 0x69 } }
+ gAmdPbsSystemConfigurationGuid = { 0xa339d746, 0xf678, 0x49b3, {
0x9f, 0xc7, 0x54, 0xce, 0x0f, 0x9d, 0xf2, 0x26 } }
+ gAmdTotalNumberOfRootBridgesGuid = { 0xfb5703f5, 0xf8a7, 0xf401, {
0x18, 0xb4, 0x3f, 0x10, 0x8d, 0xeb, 0x26, 0x12 } }
+ gApSyncFlagNvVariableGuid = { 0xad3f6761, 0xf0a3, 0x46c8, {
0xa4, 0xcb, 0x19, 0xb7, 0x0f, 0xfd, 0xb3, 0x05 } }
+ gAmdMemoryInfoHobGuid = { 0x1bce3d14, 0xa5fe, 0x4a0b, {
0x9a, 0x8d, 0x69, 0xca, 0x5d, 0x98, 0x38, 0xd3 } }
+ gAmdPspApobHobGuid = { 0x30b174f3, 0x7712, 0x4cca, {
0xbd, 0x13, 0xd0, 0xb8, 0xa8, 0x80, 0x19, 0x97 } }
+
+[Protocols]
+ gPspFlashAccSmmCommReadyProtocolGuid = { 0x9f373486, 0xda76, 0x4c9f, {
0x81, 0x55, 0x6c, 0xcd, 0xdb, 0x0b, 0x0b, 0x04 } }
+ gAmdPspFtpmProtocolGuid = { 0xac234e04, 0xb036, 0x476c, {
0x91, 0x66, 0xbe, 0x47, 0x52, 0xa0, 0x95, 0x09 } }
+ gFchInitDonePolicyProtocolGuid = { 0xc63c0c73, 0xf612, 0x4c02, {
0x84, 0xa3, 0xc6, 0x40, 0xad, 0x0b, 0xa6, 0x22 } }
+ gAmdCapsuleSmmHookProtocolGuid = { 0x4fc43bbe, 0x1433, 0x4951, {
0xac, 0x2d, 0x0d, 0x01, 0xfe, 0xc0, 0x0e, 0xb1 } }
+ gAmdCpmAllPciIoProtocolsInstalledProtocolGuid = { 0x676D7012, 0x139B,
0x485A, { 0x96, 0xF1, 0x98, 0x6F, 0xC4, 0x8A, 0x86, 0x4B } }
+ gAmdFspSetupTableInitDoneGuid = { 0xef5394c6, 0x566d, 0x440f, {
0x9d, 0x05, 0xc0, 0xa3, 0x2c, 0xb9, 0x33, 0x58 } }
+
+[Ppis]
+ gAmdMemoryInfoHobPpiGuid = { 0xba16e587, 0x1d66, 0x41b7, {
0x9b, 0x52, 0xca, 0x4f, 0x2c, 0xad, 0x0d, 0xc8 } }
+ gAmdPspFtpmPpiGuid = { 0x91774185, 0xf72d, 0x467e, {
0x93, 0x39, 0xe0, 0x08, 0xdb, 0xae, 0x0e, 0x14 } }
+ gAmdPspFtpmFactoryResetPpiGuid = { 0x9c98130a, 0x8921, 0x45eb, {
0x86, 0xf3, 0x16, 0x04, 0x35, 0xc7, 0xc6, 0x40 } }
+ gCapsuleUpdateDetectedPpiGuid = { 0x745dfc73, 0xc401, 0x4ced, {
0x8d, 0x3b, 0x1a, 0x82, 0xf3, 0xda, 0xdc, 0xf8 } }
+ gAmdCpmTablePpiGuid = { 0xd71cf893, 0xa8b5, 0x49d3, {
0xa2, 0x1b, 0x31, 0xe2, 0xf5, 0xc4, 0xa7, 0x47 } }
+
+[PcdsFixedAtBuild]
+
gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemBeforePciRestoreSwSmi|0xEA|UINT8|0x0002F010
+
gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemAfterPciRestoreSwSmi|0xD4|UINT8|0x0002F011
+
gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr|0x408|UINT16|0x0002F006
+ gAmdCpmPkgTokenSpaceGuid.AcpiRestoreSwSmi|0xE3|UINT8|0x00000040
+
+[PcdsDynamicEx]
+ ## Common
+
gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdS3LibPrivateDataAddress|0|UINT64|0x00027000
+
gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdSmmCommunicationAddress|0|UINT64|0x00027001
+
gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdS3LibTableAddress|0|UINT64|0x00027002
+
gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdS3LibTableSize|0x4000|UINT64|0x00027003
+
gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdFabricResourceDefaultSizePtr|0|UINT64|0x00DF0000
+
+ ## Setup solution
+
gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdFspSetupTableInitNeedsReset|FALSE|BOOLEAN|0xFE000000
+ #Note: system TPM config, SBIOS needs to set the value in PEI phase
+
gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdPspSystemTpmConfig|0x1|UINT8|0x00040024
+
gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgSmiCmdPortAddr|0xB0|UINT16|0x0003FFC0
\ No newline at end of file
diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AGESA.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AGESA.h
new file mode 100644
index 0000000000..de088b21c4
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AGESA.h
@@ -0,0 +1,35 @@
+/** @file
+ Common AMD header file
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include "AMD.h"
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG 0xC0010010ul
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
+#define HWCR 0xC0010015ul
+#define NB_CFG 0xC001001Ful
+
+// CPU Build Configuration structures and definitions
+
+#define AMD_AP_MTRR_FIX64k_00000 0x00000250ul
+#define AMD_AP_MTRR_FIX16k_80000 0x00000258ul
+#define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul
+#define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul
+#define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul
+#define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul
+#define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul
+#define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul
+#define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul
+#define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul
+#define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful
+#define CPU_LIST_TERMINAL 0xFFFFFFFFul
+
+#endif // _AGESA_H_
diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AMD.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AMD.h
new file mode 100644
index 0000000000..7f3727bd4b
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AMD.h
@@ -0,0 +1,189 @@
+/** @file
+ Common AMD header file
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event. Status other
than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+ AGESA_SUCCESS = 0, ///< 0 -The service completed normally. Info
may be logged.
+ AGESA_UNSUPPORTED, ///< 1 - The dispatcher or create struct had
an unimplemented function requested.
+ ///< Not logged.
+ AGESA_BOUNDS_CHK, ///< 2 - A dynamic parameter was out of range
and the service was not provided.
+ ///< Example, memory address not installed, heap buffer handle not
found.
+ ///< Not Logged.
+ AGESA_SYNC_MORE_DATA, ///< 3 - More data is available from PSP
communications
+ AGESA_SYNC_SLAVE_ASSERT, ///< 4 - Slave is at an ASSERT (used in ABL)
+ // AGESA_STATUS of greater severity (the ones below this line), always have
a log entry available.
+ AGESA_ALERT, ///< 5 - An observed condition, but no loss
of function. See Log.
+ AGESA_WARNING, ///< 6 - Possible or minor loss of
function. See Log.
+ AGESA_ERROR, ///< 7 - Significant loss of function, boot
may be possible. See Log.
+ AGESA_CRITICAL, ///< 8 - Continue boot only to notify user.
See Log.
+ AGESA_FATAL, ///< 9 - Halt booting. See Log, however
Fatal errors pertaining to heap problems
+ ///< may not be able to reliably produce log events.
+ AGESA_OC_FATAL, ///< 10 - Halt booting. Critical Memory
Overclock failure.
+ AGESA_SKIP_ERROR, ///< 11 - Error, Skip init steps.
+ AgesaStatusMax ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined
by the host environment.
+ *
+ * @param[in] Function The specific callout function being invoked.
+ * @param[in] FcnData Function specific data item.
+ * @param[in,out] ConfigPtr Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+ IN UINT32 Function,
+ IN UINTN FcnData,
+ IN OUT VOID *ConfigPtr
+ );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (
+ VOID *ConfigPtr
+ );
+typedef AGESA_STATUS (*MODULE_ENTRY) (
+ VOID *ConfigPtr
+ );
+
+/// This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+ PreMemHeap = 0, ///< Create heap
in cache.
+ PostMemDram, ///< Create heap
in memory.
+ ByHost ///< Create heap
by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to
specify the data size
+typedef enum ACCESS_WIDTH {
+ AccessWidthNone = 0, ///< dummy access
width
+ AccessWidth8 = 1, ///< Access width
is 8 bits.
+ AccessWidth16, ///< Access width
is 16 bits.
+ AccessWidth32, ///< Access width
is 32 bits.
+ AccessWidth64, ///< Access width
is 64 bits.
+
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits
data.
+ AccessS3SaveWidth16, ///< Save 16 bits
data.
+ AccessS3SaveWidth32, ///< Save 32 bits
data.
+ AccessS3SaveWidth64, ///< Save 64 bits
data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+ // AGESA BASIC FUNCTIONS
+ AMD_INIT_RECOVERY = 0x00020000, ///<
AmdInitRecovery entry point handle
+ AMD_CREATE_STRUCT, ///<
AmdCreateStruct handle
+ AMD_INIT_EARLY, ///< AmdInitEarly
entry point handle
+ AMD_INIT_ENV, ///< AmdInitEnv
entry point handle
+ AMD_INIT_LATE, ///< AmdInitLate
entry point handle
+ AMD_INIT_MID, ///< AmdInitMid
entry point handle
+ AMD_INIT_POST, ///< AmdInitPost
entry point handle
+ AMD_INIT_RESET, ///< AmdInitReset
entry point handle
+ AMD_INIT_RESUME, ///< AmdInitResume
entry point handle
+ AMD_RELEASE_STRUCT, ///<
AmdReleaseStruct handle
+ AMD_S3LATE_RESTORE, ///<
AmdS3LateRestore entry point handle
+ AMD_GET_APIC_ID, ///< AmdGetApicId
entry point handle
+ AMD_GET_PCI_ADDRESS, ///<
AmdGetPciAddress entry point handle
+ AMD_IDENTIFY_CORE, ///<
AmdIdentifyCore general service handle
+ AMD_READ_EVENT_LOG, ///<
AmdReadEventLog general service handle
+ AMD_GET_EXECACHE_SIZE, ///<
AmdGetAvailableExeCacheSize general service handle
+ AMD_LATE_RUN_AP_TASK, ///<
AmdLateRunApTask entry point handle
+ AMD_IDENTIFY_DIMMS, ///<
AmdIdentifyDimm general service handle
+ AMD_GET_2D_DATA_EYE, ///<
AmdGet2DDataEye general service handle
+ AMD_S3FINAL_RESTORE, ///<
AmdS3FinalRestore entry point handle
+ AMD_INIT_RTB ///< AmdInitRtb
entry point handle
+} AGESA_STRUCT_NAME;
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+ IN UINT32 ImageBasePtr; ///< The AGESA Image base
address.
+ IN UINT32 Func; ///< The service desired
+ IN UINT32 AltImageBasePtr; ///< Alternate Image
location
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
+ IN UINT8 HeapStatus; ///< For heap status from
boot time slide.
+ IN UINT64 HeapBasePtr; ///< Location of the heap
+ IN OUT UINT8 Reserved[7]; ///< This space is
reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+/// Create Struct Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration
header
+ IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer
allocation
+ IN OUT UINT32 NewStructSize; ///< The size of the
allocated data, in for ByHost, else out only.
+ IN OUT VOID *NewStructPtr; ///< The struct for the
service.
+ ///< The struct to init for
ByHost allocation,
+ ///< the initialized struct
on return.
+} AMD_INTERFACE_PARAMS;
+
+/// AGESA Binary module header structure
+typedef struct {
+ IN UINT32 Signature; ///< Binary Signature
+ IN CHAR8 CreatorID[8]; ///< 8 characters ID
+ IN CHAR8 Version[12]; ///< 12 characters version
+ IN UINT32 ModuleInfoOffset; ///< Offset of module
+ IN UINT32 EntryPointAddress; ///< Entry address
+ IN UINT32 ImageBase; ///< Image base
+ IN UINT32 RelocTableOffset; ///< Relocate Table offset
+ IN UINT32 ImageSize; ///< Size
+ IN UINT16 Checksum; ///< Checksum
+ IN UINT8 ImageType; ///< Type
+ IN UINT8 V_Reserved; ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+ IN UINT32 ModuleHeaderSignature; ///< Module signature
+ IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
+ IN CHAR8 ModuleVersion[12]; ///< 12 characters
version
+ IN VOID *ModuleDispatcher; ///< A pointer point
to dispatcher
+ IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module
header link
+} AMD_MODULE_HEADER;
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+ IN CHAR8 Signature[8]; ///< code header Signature
+ IN CHAR8 ComponentName[16]; ///< 16 character name of
the code module
+ IN CHAR8 Version[12]; ///< 12 character version
string
+ IN CHAR8 TerminatorNull; ///< null terminated string
+ IN CHAR8 VerReserved[7]; ///< reserved space
+} AMD_CODE_HEADER;
+
+// SBDFO - Segment Bus Device Function Offset
+// 31:28 Segment (4-bits)
+// 27:20 Bus (8-bits)
+// 19:15 Device (5-bits)
+// 14:12 Function(3-bits)
+// 11:00 Offset (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) |
(((UINT32) (Bus)) << 20) |\
+ (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) |
((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFFul
+
+/// CPUID data received registers format
+typedef struct {
+ OUT UINT32 EAX_Reg; ///< CPUID instruction
result in EAX
+ OUT UINT32 EBX_Reg; ///< CPUID instruction
result in EBX
+ OUT UINT32 ECX_Reg; ///< CPUID instruction
result in ECX
+ OUT UINT32 EDX_Reg; ///< CPUID instruction
result in EDX
+} CPUID_DATA;
+
+// Topology Services definitions and macros
+#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
+
+#endif // _AMD_H_
diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AmdPspDirectory.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AmdPspDirectory.h
new file mode 100644
index 0000000000..06d4673be8
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/AmdPspDirectory.h
@@ -0,0 +1,55 @@
+/** @file
+ AMD Psp Directory header file
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _AMD_PSP_DIR_H_
+#define _AMD_PSP_DIR_H_
+
+#pragma pack (push, 1)
+#define PSP_DIRECTORY_HEADER_SIGNATURE 0x50535024ul ///< $PSP
+#define PSP_LV2_DIRECTORY_HEADER_SIGNATURE 0x324C5024ul ///< $PL2
+/// Define structure for PSP directory
+typedef struct {
+ UINT32 Cookie; ///< "$PSP"
+ UINT32 Checksum; ///< 32 bit CRC of header items below and the entire
table
+ UINT32 TotalEntries; ///< Number of PSP Entries
+ UINT32 Reserved; ///< Unused
+} PSP_DIRECTORY_HEADER;
+
+typedef struct {
+ UINT32 Type : 8; ///< Type of PSP Directory entry
+ UINT32 SubProgram : 8; ///< Specify the SubProgram
+ UINT32 RomId : 2; ///< Specify the ROM ID
+ UINT32 Reserved : 14; ///< Reserved
+} PSP_DIRECTORY_ENTRY_TYPE_FIELD;
+
+typedef union {
+ PSP_DIRECTORY_ENTRY_TYPE_FIELD Field; // Definition of each filed
+ UINT32 Value; // Group it as 32bits Int
+} PSP_DIRECTORY_ENTRY_TYPE;
+
+enum _PSP_DIRECTORY_ENTRY_TYPE {
+ PSP_REGION_A_DIR = 0x48, ///< PSP entry points to
PSP DIR in Region A
+ PSP_REGION_B_DIR = 0x4A, ///< PSP entry points to
PSP DIR in Region B
+};
+
+/// Structure for PSP Entry
+typedef struct {
+ PSP_DIRECTORY_ENTRY_TYPE Type; ///< Type of PSP entry; 32 bit long
+ UINT32 Size; ///< Size of PSP Entry in bytes
+ UINT64 Location; ///< Location of PSP Entry (byte
offset from start of SPI-ROM)
+} PSP_DIRECTORY_ENTRY;
+
+/// Structure for PSP directory
+typedef struct {
+ PSP_DIRECTORY_HEADER Header; ///< PSP directory header
+ PSP_DIRECTORY_ENTRY PspEntry[1]; ///< Array of PSP entries each
pointing to a binary in SPI flash
+ ///< The actual size of this array
comes from the
+ ///< header
(PSP_DIRECTORY.Header.TotalEntries)
+} PSP_DIRECTORY;
+
+#pragma pack (pop)
+#endif //_AMD_PSP_DIR_H_
diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/FchRegistersCommon.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/FchRegistersCommon.h
new file mode 100644
index 0000000000..6079fcab75
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/FchRegistersCommon.h
@@ -0,0 +1,23 @@
+/** @file
+ Implements FchRegistersCommon.h
+
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#define R_FCH_ACPI_PM1_STATUS 0x00
+#define R_FCH_ACPI_PM1_ENABLE 0x02
+#define R_FCH_ACPI_PM_CONTROL 0x04
+#define ACPI_MMIO_BASE 0xFED80000ul
+#define SMI_BASE 0x200 // DWORD
+#define PMIO_BASE 0x300 // DWORD
+#define FCH_SMI_REG80 0x80 // SmiStatus0
+#define FCH_SMI_REG84 0x84 // SmiStatus1
+#define FCH_SMI_REG88 0x88 // SmiStatus2
+#define FCH_SMI_REG8C 0x8C // SmiStatus3
+#define FCH_SMI_REG90 0x90 // SmiStatus4
+#define FCH_SMI_REG98 0x98 // SmiTrig
+#define FCH_SMI_REGA0 0xA0
+#define FCH_SMI_REGB0 0xB0
+#define FCH_SMI_REGC4 0xC4
+#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk
\ No newline at end of file
diff --git
a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Guid/AmdMemoryInfoHob.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Guid/AmdMemoryInfoHob.h
new file mode 100644
index 0000000000..4815dc4d6e
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Guid/AmdMemoryInfoHob.h
@@ -0,0 +1,51 @@
+/** @file
+ AMD Memory Info Hob Definition
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _AMD_MEMORY_INFO_HOB_H_
+#define _AMD_MEMORY_INFO_HOB_H_
+
+extern EFI_GUID gAmdMemoryInfoHobGuid;
+
+#pragma pack (push, 1)
+
+/// Memory descriptor structure for each memory rang
+typedef struct {
+ UINT64 Base; ///< Base address of memory rang
+ UINT64 Size; ///< Size of memory rang
+ UINT32 Attribute; ///< Attribute of memory rang
+ UINT32 Reserved; ///< For alignment purpose
+} AMD_MEMORY_RANGE_DESCRIPTOR;
+
+#define AMD_MEMORY_ATTRIBUTE_AVAILABLE 0x1
+#define AMD_MEMORY_ATTRIBUTE_UMA 0x2
+#define AMD_MEMORY_ATTRIBUTE_MMIO 0x3
+#define AMD_MEMORY_ATTRIBUTE_RESERVED 0x4
+#define AMD_MEMORY_ATTRIBUTE_GPUMEM 0x5
+#define AMD_MEMORY_ATTRIBUTE_GPU_SP 0x6
+#define AMD_MEMORY_ATTRIBUTE_GPU_RESERVED 0x7
+#define AMD_MEMORY_ATTRIBUTE_GPU_RESERVED_TMR 0x8
+#define AMD_MEMORY_ATTRIBUTE_Reserved_SmuFeatures 0x9
+
+/// Memory info HOB structure
+typedef struct {
+ UINT32 Version; ///< Version of HOB
structure
+ BOOLEAN AmdMemoryVddioValid; ///< This field
determines if Vddio is valid
+ UINT16 AmdMemoryVddio; ///< Vddio Voltage
+ BOOLEAN AmdMemoryVddpVddrValid; ///< This field
determines if VddpVddr is valid
+ UINT8 AmdMemoryVddpVddr; ///< VddpVddr voltage
+ BOOLEAN AmdMemoryFrequencyValid; ///< Memory
Frequency Valid
+ UINT32 AmdMemoryFrequency; ///< Memory Frquency
+ UINT32 AmdMemoryDdrMaxRate; ///< Memory
DdrMaxRate
+ UINT32 NumberOfDescriptor; ///< Number of
memory range descriptor
+ AMD_MEMORY_RANGE_DESCRIPTOR Ranges[1]; ///< Memory ranges
array
+} AMD_MEMORY_INFO_HOB;
+
+#pragma pack (pop)
+
+#define AMD_MEMORY_INFO_HOB_VERISION 0x00000110ul // Ver: 00.00.01.10
+
+#endif // _AMD_MEMORY_INFO_HOB_H_
diff --git
a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspBaseLibV2.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspBaseLibV2.h
new file mode 100644
index 0000000000..198df537c1
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspBaseLibV2.h
@@ -0,0 +1,248 @@
+/** @file
+ AMD Psp Base Lib
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _AMD_PSP_BASELIB_V2_H_
+#define _AMD_PSP_BASELIB_V2_H_
+
+#include <AMD.h>
+#include <AmdPspDirectory.h>
+
+#define PSP_MAILBOX_BASE 0x70 ///< Mailbox
base offset on PCIe BAR
+#define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus
Offset
+#define IS_ADDRESS_MODE_1(a) (((a) >> 62) == 1 ? TRUE : FALSE) // relative to
BIOS image base 0
+#define IS_ADDRESS_MODE_2(a) (((a) >> 62) == 2 ? TRUE : FALSE) // relative to
current directory header
+#define IS_ADDRESS_MODE_3(a) (((a) >> 62) == 3 ? TRUE : FALSE) // relative to
active image slot address (as of now, active image slot address is equal to PSP
L2 base address)
+#define IS_SPI_OFFSET(a) (((a) & 0xFF000000) != 0xFF000000 ? TRUE : FALSE)
+
+#define MaxDirEntryNumber 64
+#define MaxPspDirSize sizeof(PSP_DIRECTORY_HEADER) +
(sizeof(BIOS_DIRECTORY_ENTRY) * MaxDirEntryNumber)
+#define MAX_IMAGE_SLOT_COUNT 32
+
+#define ALIGNMENT_4K BASE_4KB
+#define ALIGN_CHECK(addr, alignment) ((((UINTN)(addr)) & ((alignment) - 1))
== 0)
+#define ALIGN_4K_CHECK(addr) ALIGN_CHECK((addr), ALIGNMENT_4K)
+
+#define IS_VALID_ADDR32(addr) (((UINT32)(addr) != 0) && (UINT32)(addr) !=
0xFFFFFFFF)
+#define MaxImageSlotInfoSize sizeof(IMAGE_SLOT_INFO)
+//
+// offset between Active Image Slot address and PSP L2 Directory
+//
+#define PSP_L2_DIR_OFFSET 0
+
+#pragma pack (push, 1)
+
+///
+/// X86 to PSP Buffer which start mapping from C2PMSG_28
+///
+typedef volatile struct {
+ UINT32 Status : 16; ///< Set by the target to indicate
the execution status of last command
+ UINT32 CommandId : 8; ///< Command ID set by host
+ UINT32 Reserved : 5; ///< Reserved
+ UINT32 ResetRequired : 1; // < Set by the target to indicate
that the host has to execute warm reset if corrupted detected in tOS
+ UINT32 Recovery : 1; ///< Set by the target to indicate
that the host has to execute FW recovery sequence
+ UINT32 Ready : 1; ///< Set by the target to indicate
the mailbox interface state.
+} PSP_MBOX_V2_CMD_EXT;
+
+typedef volatile union {
+ IN UINT32 Value; ///< Cmd register value
+ IN PSP_MBOX_V2_CMD_EXT Field; ///< Extended Cmd register
with field definition
+} PSP_MBOX_V2_CMD;
+
+typedef volatile struct {
+ PSP_MBOX_V2_CMD Cmd;
+ UINT64 Buffer; ///< 64 bit Ponter to memory with
additional parameter.
+} PSP_MBOX_V2;
+
+#define FIRMWARE_TABLE_SIGNATURE 0x55AA55AAul
+/// Define the structure OEM signature table
+typedef struct _FIRMWARE_ENTRY_TABLEV2 {
+ UINT32 Signature; ///< 0x00 Signature should be 0x55AA55AAul
+ UINT32 ImcRomBase; ///< 0x04 Base Address for Imc Firmware
+ UINT32 GecRomBase; ///< 0x08 Base Address for Gmc Firmware
+ UINT32 XHCRomBase; ///< 0x0C Base Address for XHCI Firmware
+ UINT32 LegacyPspDirBase; ///< 0x10 Base Address of PSP directory for
legacy program (ML, BP, CZ, BR, ST)
+ UINT32 PspDirBase; ///< 0x14 Base Address for PSP directory
+ UINT32 ZpBiosDirBase; ///< 0x18 Base Address for ZP BIOS directory
+ UINT32 RvBiosDirBase; ///< 0x1C Base Address for RV BIOS directory
+ UINT32 SspBiosDirBase; ///< 0x20 Base Address for RV BIOS directory
+ UINT32 Config; ///< 0x24 reserved for EFS configuration
+ UINT32 NewBiosDirBase; ///< 0x28 Generic Base address for all program
start from RN
+ UINT32 PspDirBackupBase; ///< 0x2C Backup PSP directory address for all
programs starting from RMB
+} FIRMWARE_ENTRY_TABLEV2;
+
+/// Unified Boot BIOS Directory structure
+enum _BIOS_DIRECTORY_ENTRY_TYPE {
+ BIOS_PUBLIC_KEY = 0x05, ///< PSP entry points to BIOS
public key stored in SPI space
+ BIOS_RTM_SIGNATURE = 0x07, ///< PSP entry points to signed
BIOS RTM hash stored in SPI space
+ MAN_OS = 0x5C, ///< PSP entry points to
manageability OS binary
+ MAN_IP_LIB = 0x5D, ///< PSP entry points to
manageability proprietary IP library
+ MAN_CONFIG = 0x5E, ///< PSP entry points to
manageability configuration inforamtion
+ BIOS_APCB_INFO = 0x60, ///< Agesa PSP Customization
Block (APCB)
+ BIOS_APOB_INFO = 0x61, ///< Agesa PSP Output Block
(APOB) target location
+ BIOS_FIRMWARE = 0x62, ///< BIOS Firmware volumes
+ APOB_NV_COPY = 0x63, ///< APOB data copy on
non-volatile storage which will used by ABL during S3 resume
+ PMU_INSTRUCTION = 0x64, ///< Location field pointing to
the instruction portion of PMU firmware
+ PMU_DATA = 0x65, ///< Location field pointing to
the data portion of PMU firmware
+ UCODE_PATCH = 0x66, ///< Microcode patch
+ CORE_MCEDATA = 0x67, ///< Core MCE data
+ BIOS_APCB_INFO_BACKUP = 0x68, ///< Backup Agesa PSP
Customization Block (APCB)
+ BIOS_DIR_LV2 = 0x70, ///< BIOS entry points to Level
2 BIOS DIR
+};
+
+/// Directory type
+typedef enum _DIRECTORY_TYPE {
+ DIR_TYPE_PSP_LV2 = 0, ///< Level 2 PSP DIR
+ DIR_TYPE_BIOS_LV2 = 1, ///< Level 2 BIOS DIR
+} DIRECTORY_TYPE;
+
+/// Type attribute for BIOS Directory entry
+typedef struct {
+ UINT32 Type : 8; ///< [0:7], Type of BIOS entry
+ UINT32 RegionType : 8; ///< [8:15], 0 Normal memory, 1 TA1 memory, 2
TA2 memor
+ UINT32 BiosResetImage : 1; ///< [16], Set for SEC or EL3 fw, which will
be authenticate by PSP FW known as HVB
+ UINT32 Copy : 1; ///< [17], Copy: 1- copy BIOS image image from
source to destination 0- Set region attribute based on <ReadOnly, Source, size>
attributes
+ UINT32 ReadOnly : 1; ///< [18], 1: Set region to read-only
(applicable for ARM- TA1/TA2) 0: Set region to read/write
+ UINT32 Compressed : 1; ///< [19], 1: Compresed
+ UINT32 Instance : 4; ///< [20:23], Specify the Instance of an entry
+ UINT32 SubProgram : 3; ///< [24:26], < Specify the SubProgram
+ UINT32 RomId : 2; ///< [27:28], Specify the RomId
+ UINT32 Reserved : 3; ///< [29:31], Reserve for future use
+} TYPE_ATTRIB;
+
+/// Structure for PSP Entry
+typedef struct {
+ TYPE_ATTRIB TypeAttrib; ///< Type of PSP entry; 32 bit
long
+ UINT32 Size; ///< Size of PSP Entry in bytes
+ UINT64 Location; ///< Location of PSP Entry
(byte offset from start of SPI-ROM)
+ UINT64 Destination; ///< Destination of PSP Entry
copy to
+} BIOS_DIRECTORY_ENTRY;
+
+#define BIOS_DIRECTORY_HEADER_SIGNATURE 0x44484224ul ///< $BHD BIOS
Directory Signature
+#define BIOS_LV2_DIRECTORY_HEADER_SIGNATURE 0x324C4224ul ///< $BL2 BIOS
Directory Lv2 Signature
+/// Structure for BIOS directory
+typedef struct {
+ PSP_DIRECTORY_HEADER Header; ///< PSP directory header
+ BIOS_DIRECTORY_ENTRY BiosEntry[1]; ///< Array of PSP entries each
pointing to a binary in SPI flash
+ ///< The actual size of this array
comes from the
+ ///< header
(PSP_DIRECTORY.Header.TotalEntries)
+} BIOS_DIRECTORY;
+
+/// Structure for PSP Combo directory
+#define PSP_COMBO_DIRECTORY_COOKIE 0x50535032ul ///< 2PSP PSP Combo
Directory Signature
+#define BIOS_COMBO_DIRECTORY_COOKIE 0x44484232ul ///< "BHD2" BIOS Combo
Directory Signature
+
+typedef struct {
+ UINT32 Cookie; ///< "2PSP" or "2BHD"
+ UINT32 Checksum; ///< 32 bit CRC of header items below and the entire
table
+ UINT32 TotalEntries; ///< Number of PSP Entries
+ UINT32 LookUpMode; ///< 0 - Dynamic look up through all entries, 1 -
PSP/chip ID match.
+ UINT8 Reserved[16]; ///< Reserved
+} COMBO_DIRECTORY_HEADER;
+
+/// Structure for PSP Combo directory entry
+typedef struct {
+ UINT32 IdSelect; ///< 0 - Compare PSP ID, 1 - Compare chip family ID
+ UINT32 Id; ///< 32-bit Chip/PSP ID
+ UINT64 DirTableAddr; ///< Point to PSP directory table (level 2)
+} COMBO_DIRECTORY_ENTRY;
+
+/**
+ * @brief PSP/BIOS entry region with start address and size
+ *
+ */
+typedef struct {
+ UINT64 Address;
+ UINT32 Size;
+} ENTRY_REGION;
+
+/// RECOVERY_REASON_VERSION
+typedef enum {
+ RECOVERY_REASON_VERSION_IGNORE = 0xFFFFFFFFul, // before RN
+ RECOVERY_REASON_VERSION_1 = 1, // RN, CZN
+ RECOVERY_REASON_VERSION_2 = 2, // Starting from VN
+} RECOVERY_REASON_VERSION;
+
+/// PSP Recovery Reason V1
+typedef struct {
+ UINT32 EntryType : 16; ///< [0:15], Entry type ID of the binary in
PSP/BIOS entry whose corruption caused recovery
+ UINT32 DirectoryLevel : 2; ///< [16:17],b'01--The entry is from PSP
directory L1
+ /// b'10--The entry is from PSP
directory L2
+ /// b'11--The entry is from BIOS
directory L2
+ UINT32 Instance : 4; ///< [18:21],the instance number of the
corrupted entry
+ UINT32 PartitionNumber : 3; ///< [22:24],Which partition this log is from
+ UINT32 Reserved : 7; ///< [25:31] Reserve for future use
+} RECOVERY_REASON_V1;
+
+/// PSP Recovery Reason V2
+typedef struct {
+ UINT32 EntryType : 8; ///< [0:7], Entry type ID of the binary in
PSP/BIOS entry whose corruption caused recovery
+ UINT32 Instance : 4; ///< [8:11],the instance number of the
corrupted entry
+ UINT32 SubProgram : 4; ///< [12:15], SubProgram
+ UINT32 DirectoryLevel : 4; ///< [16:19],b'01--The entry is from PSP
directory L1
+ /// b'10--The entry is from PSP
directory L2
+ /// b'11--The entry is from BIOS
directory L2
+ /// b'100--PSP L1 directory header
+ /// b'101--PSP L2 directory header
+ /// b'110--BIOS directory L2 header
+ /// b'111--Image Slot Header
+ UINT32 Reserved : 2; ///< [20:21], Reserved
+ UINT32 PartitionNumber : 3; ///< [22:24],Which partition this log is from
+ UINT32 Reserved2 : 7; ///< [25:31] Reserve for future use
+} RECOVERY_REASON_V2;
+
+#define VN_PSP_CHIP_ID 0xBC0B0800 ///< VN Chip ID in combo structure
+
+typedef struct {
+ COMBO_DIRECTORY_HEADER Header; ///< PSP Combo directory header
+ COMBO_DIRECTORY_ENTRY ComboEntry[1]; ///< Array of PSP combo entries
each pointing to level 2 PSP Direcotry header
+} COMBO_DIRECTORY;
+
+#define IMAGE_SLOT_PRIORITY_UNBOOTABLE 0
+/// Structure for image slot entry, only used in family VN & MR
+// It also used as structure to store ISH generic information accross programs
+typedef struct {
+ UINT32 Priority;
+ UINT32 UpdateRetries;
+ UINT32 GlitchRetries;
+ UINT32 ImageSlotAddr;
+} IMAGE_SLOT_HEADER;
+
+// Structure for image slot entry, start use from RMB
+// Major changes:
+// 1. Add CRC checksum
+// 2. Add PSPID to support combo, w/o combo directory
+// 3. Increased max entry number, 8 -> 32 (support up to 16 SOCs)
+// 4. Increased L1 as well as pointer in EFS (support multiple SOC image flash
programming)
+typedef struct {
+ UINT32 CheckSum; // [0x0000]
+ UINT32 Priority; // [0x0004]
+ UINT32 UpdateRetries; // [0x0008]
+ UINT8 GlitchRetries; // [0x000C]
+ UINT8 Reserved[3]; // [0x000D]
+ UINT32 ImageSlotAddr; // [0x0010]
+ UINT32 PspId; // [0x0014]
+ UINT32 SlotMaxSize; // [0x0018]
+ UINT32 Reserved_1; // [0x001C]
+} IMAGE_SLOT_HEADER_V2; // [0x0020]
+
+typedef struct {
+ UINT32 SlotCount; // the slot
count in the system
+ UINT8 BootableSlotCount; // the
bootable slot count in the system
+ UINT8 BootableSlotArray[MAX_IMAGE_SLOT_COUNT]; // bootable
slot index array
+ UINT8 UnbootableSlotCount; // the
unbootable slot count in the system
+ UINT8 UnbootableSlotArray[MAX_IMAGE_SLOT_COUNT]; //
unbootable slot index array
+ UINT8 SlotAIndex; // index of
slot with highest priority
+ IMAGE_SLOT_HEADER SlotAHeader; // slot
header with highest priority
+ UINT8 SlotBIndex; // index of
slot with second highest priority
+ IMAGE_SLOT_HEADER SlotBHeader; // slot
header with second highest priority
+} IMAGE_SLOT_INFO;
+
+#pragma pack (pop)
+
+#define INSTANCE_IGNORED 0xFF
+#define SUBPROGRAM_IGNORED 0xFF
+#endif // _AMD_LIB_H_
diff --git
a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspCommonLib.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspCommonLib.h
new file mode 100644
index 0000000000..eb0f09dd58
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspCommonLib.h
@@ -0,0 +1,29 @@
+/** @file
+ AMD Psp Common Library header file
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _AMD_PSPCOMMONLIB_H_
+#define _AMD_PSPCOMMONLIB_H_
+
+#include <AmdPspDirectory.h>
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+
*----------------------------------------------------------------------------------------
+ */
+
+#define TCG_EVENT_BASE_AMD ((TCG_EVENTTYPE) 0x8000)
+#define TCG_EVENT_BASE_AMD_BIOS (TCG_EVENT_BASE_AMD + 0x400)
+#define TCG_EVENT_AMD_BIOS_TSME_MEASUREMENT (TCG_EVENT_BASE_AMD_BIOS + 1)
+
+BOOLEAN
+GetFtpmControlArea (
+ IN OUT VOID **FtpmControlArea
+ );
+
+#define PSPLIB_WAIT_INFINITELY 0xFFFFFFFFL
+
+#endif // _AMD_PSPCOMMONLIB_H_
diff --git
a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspFtpmLib.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspFtpmLib.h
new file mode 100644
index 0000000000..2bd4dcefaa
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Library/AmdPspFtpmLib.h
@@ -0,0 +1,94 @@
+/** @file
+ AMD Psp Ftpm Library header file
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PSP_FTPM_LIB_H_
+#define _PSP_FTPM_LIB_H_
+#include <IndustryStandard/Acpi30.h>
+
+#define PSP_DEBUG_ENABLE 0
+
+#define HSP_VIDDID 0x163E1022
+#define HSP_TEMP_BAR0_SIZE 0x10000 // 64KB is enough
+
+//
+/// 1MB @todo check. Also move this to common header file and make it
customizable
+/// perhaps fed it via build option etc
+#define FTPM_COMMAND_BUFFER_SIZE (16*1024)
+#define FTPM_RESPONSE_BUFFER_SIZE (16*1024)
+
+/* SYSTEM_TPM_CONFIG_VAL
+ * Value range for APCB_TOKEN_UID_PSP_SYSTEM_TPM_CONFIG
+ */
+typedef enum {
+ SYSTEM_TPM_CONFIG_DTPM = 0x00, ///< dTPM
+ SYSTEM_TPM_CONFIG_PSP_FTPM = 0x01, ///< PSP FTPM
+ SYSTEM_TPM_CONFIG_HSP_FTPM = 0x02, ///< HSP FTPM
+ SYSTEM_TPM_CONFIG_NONE = 0xFF, ///< None of TPM
+} SYSTEM_TPM_CONFIG_VAL;
+
+#pragma pack (push, 1)
+/// Define TPM_2_CONTROL_AREA
+typedef struct {
+ // Interface Identifier
+ volatile UINT64 InterfaceIdentifier; ///< Interface Identifier
+
+ // TPM2 Control Area Extension
+ volatile UINT32 Clear; ///< Clear
+ volatile UINT32 RemainingBytes; ///< RemainingBytes
+ volatile UINT32 StatusReserved; ///< StatusReserved
+ volatile UINT32 StatusError; ///< StatusError
+ volatile UINT32 StatusCancel; ///< StatusCancel
+ volatile UINT32 StatusStart; ///< StatusStart
+ UINT64 InterruptControl; ///< InterruptControl
+ UINT32 CommandSize; ///< CommandSize
+ EFI_PHYSICAL_ADDRESS CommandAddress; ///< CommandAddress
+ UINT32 ResponseSize; ///< ResponseSize
+ EFI_PHYSICAL_ADDRESS ResponseAddress; ///< ResponseAddress
+ // Memory Absent command/response buffer
+ volatile UINT32 CmdRespHWBuffer; ///< Cmd/Rsp HW Buffer
+} TPM2_CONTROL_AREA;
+
+#pragma pack (pop)
+
+/**
+ GET TPM related Info
+
+ @param[in,out] FtpmStatus Used to hold more detail info (Unused
Currently)
+
+ @return EFI_SUCCESS Ftpm function supported
+ @return EFI_UNSUPPORTED Ftpm function unsupported
+
+**/
+EFI_STATUS
+FtpmGetInfo (
+ IN OUT UINTN *FtpmStatus
+ );
+
+/**
+ Execute a TPM command
+
+ @param[in] CommandBuffer Point to the TPM command buffer
+ @param[in] CommandSize Size of the TPM command buffer
+ @param[in] ResponseBuffer Point to the TPM response buffer
+ @param[in] ResponseSize Size of the TPM response buffer
+
+ @return EFI_SUCCESS Command executed successfully
+ @return EFI_UNSUPPORTED Device unsupported
+ @return EFI_TIMEOUT Command fail due the time out
+ @return EFI_DEVICE_ERROR Command fail due the error status
set
+ @return EFI_BUFFER_TOO_SMALL Response buffer too small to hold
the response
+
+**/
+EFI_STATUS
+FtpmExecuteCommand (
+ IN VOID *CommandBuffer,
+ IN UINT32 CommandSize,
+ IN OUT VOID *ResponseBuffer,
+ IN OUT UINT32 *ResponseSize
+ );
+
+#endif //_PSP_FTPM_LIB_H_
diff --git a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h
new file mode 100644
index 0000000000..5fe59719fb
--- /dev/null
+++ b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Ppi/AmdPspFtpmPpi.h
@@ -0,0 +1,80 @@
+/** @file
+ AMD Psp Ftpm Ppi Header
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PSP_FTPM_PPI_H_
+#define _PSP_FTPM_PPI_H_
+#include <Uefi.h>
+typedef struct _PSP_FTPM_PPI PSP_FTPM_PPI;
+
+/// Define function prototype: Execute a TPM command
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_EXECUTE)(
+ IN PSP_FTPM_PPI *This,
+ IN VOID *CommandBuffer,
+ IN UINTN CommandSize,
+ IN OUT VOID *ResponseBuffer,
+ IN OUT UINTN *ResponseSize
+ );
+
+/// Define function prototype: GET TPM related Info
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_CHECK_STATUS)(
+ IN PSP_FTPM_PPI *This,
+ IN OUT UINTN *FtpmStatus
+ );
+
+/// Define function prototype: Send a TPM command
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_SEND_COMMAND)(
+ IN PSP_FTPM_PPI *This,
+ IN VOID *CommandBuffer,
+ IN UINTN CommandSize
+ );
+
+/// Define function prototype: Get a TPM command's response
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_GET_RESPONSE)(
+ IN PSP_FTPM_PPI *This,
+ IN OUT VOID *ResponseBuffer,
+ IN OUT UINTN *ResponseSize
+ );
+
+/// Define function prototype: Get TCG Logs
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_GET_TCG_LOGS)(
+ IN PSP_FTPM_PPI *This,
+ IN OUT VOID *ResponseBuffer,
+ IN OUT UINTN *ResponseSize
+ );
+
+//
+// PPI prototype
+//
+// Defines PSP_FTPM_PPI. This PPI is used to get Ftpm info
+// Send TPM command, Get TPM command's response, Execute TPM command(Include
send & get response)
+
+/// Define PSP_FTPM_PPI
+typedef struct _PSP_FTPM_PPI {
+ FTPM_EXECUTE Execute; ///< Execute TPM
command, include send & get response
+ FTPM_CHECK_STATUS CheckStatus; ///< Check TPM Status
+ FTPM_SEND_COMMAND SendCommand; ///< Send TPM command
+ FTPM_GET_RESPONSE GetResponse; ///< Get Last TPM
command response
+ FTPM_GET_TCG_LOGS GetTcgLogs; ///< Get TCG Logs
+} PSP_FTPM_PPI;
+
+extern EFI_GUID gAmdPspFtpmPpiGuid;
+extern EFI_GUID gAmdPspFtpmFactoryResetPpiGuid;
+typedef struct _PSP_FTPM_FACTORY_RESET_PPI {
+ UINT8 Version; ///< PPI Version
+} PSP_FTPM_FACTORY_RESET_PPI;
+
+#endif
diff --git
a/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Protocol/AmdPspFtpmProtocol.h
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Protocol/AmdPspFtpmProtocol.h
new file mode 100644
index 0000000000..532f6ff157
--- /dev/null
+++
b/Platform/AMD/VanGoghBoard/AgesaPublic/Include/Protocol/AmdPspFtpmProtocol.h
@@ -0,0 +1,112 @@
+/** @file
+ AMD Psp Ftpm Protocol Header
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FTPM_PROTOCOL_H_
+#define _FTPM_PROTOCOL_H_
+
+#include <Uefi.h>
+//
+// GUID definition
+//
+extern EFI_GUID gAmdPspFtpmProtocolGuid;
+
+typedef struct {
+ // C2H_TPM_L0
+ UINT64 TPM_L0_Address; // Mailbox address
+ UINT64 TPM_L0_C2H_MSG_Address; // Doorbell address CPU->HSP
+ UINT64 TPM_L0_H2C_MSG_Address; // Doorbell address HSP->CPU
+
+ // C2H_HSP_L0(VLT0)
+ UINT64 VLT0_Address; // Mailbox address
+ UINT64 VLT0_C2H_MSG_Address; // Doorbell address CPU->HSP
+ UINT64 VLT0_H2C_MSG_Address; // Doorbell address HSP->CPU
+
+ // C2H_HSP_L1(VLT1)
+ UINT64 VLT1_Address; // Mailbox address
+ UINT64 VLT1_C2H_MSG_Address; // Doorbell address CPU->HSP
+ UINT64 VLT1_HSC_MSG_Address; // Doorbell address HSP->CPU
+
+ // Interrupt Information
+ UINT8 Gsi[4]; // Gsi[0] is for HSP Channel 0 TPM
+ // Gsi[1] is for HSP Channel 1 VTL0
+ // Gsi[2] is for HSP Channel 2 VTL1
+ // Gsi[3] is reserved
+} HSP_MAILBOX_ADDRESS, *PHSP_MAILBOX_ADDRESS;
+
+typedef union {
+ HSP_MAILBOX_ADDRESS HSP_info;
+} FTPM_INFO;
+
+typedef struct _PSP_FTPM_PROTOCOL PSP_FTPM_PROTOCOL;
+
+/// Define function prototype: Execute a TPM command
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_EXECUTE)(
+ IN PSP_FTPM_PROTOCOL *This,
+ IN VOID *CommandBuffer,
+ IN UINT32 CommandSize,
+ IN OUT VOID *ResponseBuffer,
+ IN OUT UINT32 *ResponseSize
+ );
+
+/// Define function prototype: GET TPM related Info
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_CHECK_STATUS)(
+ IN PSP_FTPM_PROTOCOL *This,
+ IN OUT UINTN *FtpmStatus
+ );
+
+/// Define function prototype: Send a TPM command
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_SEND_COMMAND)(
+ IN PSP_FTPM_PROTOCOL *This,
+ IN VOID *CommandBuffer,
+ IN UINT32 CommandSize
+ );
+
+/// Define function prototype: Get a TPM command's response
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_GET_RESPONSE)(
+ IN PSP_FTPM_PROTOCOL *This,
+ IN OUT VOID *ResponseBuffer,
+ IN OUT UINT32 *ResponseSize
+ );
+
+/// Define function prototype: Get TCG Logs
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_GET_TCG_LOGS)(
+ IN PSP_FTPM_PROTOCOL *This,
+ IN OUT VOID *ResponseBuffer,
+ IN OUT UINTN *ResponseSize
+ );
+
+/// Define function prototype: Get TPM info
+typedef
+EFI_STATUS
+(EFIAPI *FTPM_GET_TPM_INFO)(
+ IN PSP_FTPM_PROTOCOL *This,
+ IN OUT VOID *FtpmInfo
+ );
+
+/// Defines PSP_FTPM_PROTOCOL. This protocol is used to get Ftpm info
+/// Send TPM command, Get TPM command's response, Execute TPM command(Include
send & get response)
+
+typedef struct _PSP_FTPM_PROTOCOL {
+ FTPM_EXECUTE Execute; ///< Execute TPM
command, include send & get response
+ FTPM_CHECK_STATUS CheckStatus; ///< Check TPM Status
+ FTPM_SEND_COMMAND SendCommand; ///< Send TPM command
+ FTPM_GET_RESPONSE GetResponse; ///< Get Last TPM
command response
+ FTPM_GET_TCG_LOGS GetTcgLogs; ///< Get TCG Logs
+ FTPM_GET_TPM_INFO GetInfo; ///< Get TPM info
+} PSP_FTPM_PROTOCOL;
+
+#endif //_FTPM_PROTOCOL_H_
--
2.31.1
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