Hi,
> + if (Cr4.Bits.LA57) {
> + if (PhysBits > 48) {
> + /*
> + * Some Intel CPUs support 5-level paging, have more than 48
> + * phys-bits but support only 4-level EPT, which effectively
> + * limits guest phys-bits to 48.
> + *
> + * AMD Processors have a different but somewhat related
> + * problem: They can handle guest phys-bits larger than 48
> + * only in case the host runs in 5-level paging mode.
> + *
> + * Until we have some way to communicate that kind of
> + * limitations from hypervisor to guest, limit phys-bits
> + * to 48 unconditionally.
> + */
So I'm looking for some communication path. One option would be to use
some bits in the KVM cpuid leaves. Another possible candidate is cpuid
leaf 0x80000008.
>From the AMD APM (revision 3.35):
CPUID Fn8000_0008_EAX Long Mode Size Identifiers
------------------------------------------------
The value returned in EAX provides information about the maximum host
and guest physical and linear address width (in bits) supported by the
processor.
Bits FieldName Description
31:24 — Reserved
23:16 GuestPhysAddrSize Maximum guest physical address size in bits.
This number applies only to guests using nested
paging. When this field is zero, refer to the
PhysAddrSize field for the maximum guest
physical address size. See “Secure Virtual
Machine” in APM Volume 2.
15:8 LinAddrSize Maximum linear address size in bits.
7:0 PhysAddrSize Maximum physical address size in bits. When
GuestPhysAddrSize is zero, this field also
indicates the maximum guest physical address
size.
The description of the GuestPhysAddrSize is somewhat vague. Is this a
value the hypervisor should use to figure how much address space it can
give to guests? Or is this a value the hypervisor can set to inform the
guest about the available address space (which would be a solution to
the problem outlined in the comment above)? Or both?
In case GuestPhysAddrSize should not be used this way: Is it possible
allocate the currently reserved bits 31:24 for that purpose?
Tom? Michael?
thanks & take care,
Gerd
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