Changes to support spec changes
1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Chiu Chasel <chasel.c...@intel.com>
Cc: Duggapu Chinni B <chinni.b.dugg...@intel.com>
Signed-off-by: Duggapu Chinni B <chinni.b.dugg...@intel.com>
---
IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 2 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 2 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 +
.../FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 1 -
.../FspSecCore/Ia32/FspApiEntryM.nasm | 1 -
.../FspSecCore/Ia32/FspApiEntryT.nasm | 70 ++++++++++++++---
.../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 11 +++
IntelFsp2Pkg/FspSecCore/SecFsp.c | 17 +++-
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 4 +-
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 78 +++++++++++++++----
IntelFsp2Pkg/Include/FspEas/FspApi.h | 5 +-
.../Include/SaveRestoreSseAvxNasm.inc | 21 +++++
IntelFsp2Pkg/IntelFsp2Pkg.dec | 5 ++
.../SecRamInitData.c | 3 +-
14 files changed, 185 insertions(+), 36 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
index cb011f99f9..cf8cb2eda9 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -63,11 +63,11 @@
[Pcd]
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES
[Ppis]
gEfiTemporaryRamSupportPpiGuid ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 8029832235..717941c33f 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -62,11 +62,11 @@
[Pcd]
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES
[Ppis]
gEfiTemporaryRamSupportPpiGuid ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e5a6eaa164..05c0d5f48b 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -51,6 +51,7 @@
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES
[Ppis]
gEfiTemporaryRamSupportPpiGuid ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
; Following are fixed PCDs
;
extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
; Following are fixed PCDs
;
extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
-extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 900126b93b..020599ba89 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -16,6 +16,7 @@
extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
+extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))
;
; Following functions will be provided in PlatformSecLib
@@ -109,7 +110,8 @@ struc LoadMicrocodeParamsFsp24
.FsptArchReserved: resb 3
.FsptArchLength: resd 1
.FspDebugHandler resq 1
- .FsptArchUpd: resd 4
+ .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is >=
3
+ .FsptArchUpd: resd 3
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resq 1
@@ -267,7 +269,7 @@ ASM_PFX(LoadMicrocodeDefault):
cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader
cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
- je Fsp24UpdHeader
+ jae Fsp24UpdHeader
jmp Fsp22UpdHeader
Fsp20UpdHeader:
@@ -405,7 +407,7 @@ CheckAddress:
cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader1
cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
- je Fsp24UpdHeader1;
+ jae Fsp24UpdHeader1;
jmp Fsp22UpdHeader1
Fsp20UpdHeader1:
@@ -497,7 +499,15 @@ ASM_PFX(EstablishStackFsp):
; Enable FSP STACK
;
mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
- add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
+ LOAD_TEMPORARY_RAM_SIZE ecx
+ add esp, ecx
+ ;
+ ; Save TemporaryRam size in PcdGlobalDataPointerAddress
+ ; which will be used in FSP-M if required.
+ ;
+ mov rax, ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))
+ mov eax, DWORD[rax]
+ mov DWORD[eax], ecx
push DATA_LEN_OF_MCUD ; Size of the data region
push 4455434Dh ; Signature of the data region 'MCUD'
@@ -506,7 +516,7 @@ ASM_PFX(EstablishStackFsp):
cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader2
cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
- je Fsp24UpdHeader2
+ jae Fsp24UpdHeader2
jmp Fsp22UpdHeader2
Fsp20UpdHeader2:
@@ -554,12 +564,13 @@ ContinueAfterUpdPush:
;
; Set ECX/EDX to the BootLoader temporary memory range
;
- mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
- mov edx, ecx
- add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
+ mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
+ LOAD_TEMPORARY_RAM_SIZE ecx
+ add edx, ecx
sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]
+ mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
- cmp ecx, edx ;If PcdFspReservedBufferSize >=
PcdTemporaryRamSize, then error.
+ cmp ecx, edx ;If PcdFspReservedBufferSize >= TemporaryRamSize,
then error.
jb EstablishStackFspSuccess
mov eax, 80000003h ;EFI_UNSUPPORTED
jmp EstablishStackFspExit
@@ -599,6 +610,47 @@ ASM_PFX(TempRamInitApi):
CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
SAVE_ECX ; save UPD param to slot 3 in xmm6
+ mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
+ mov edx, DWORD [edx]
+ ;
+ ; Read ARCH2 UPD input value.
+ ;
+ mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize]
+ ;
+ ; As per spec, if Bootloader pass zero, use Fsp defined Size
+ ; Irrespective of whether this UPD is supported or not, Fallback
+ ; to Fsp defined size if input is zero.
+ ;
+ cmp ebx, 0
+ jz UseTemporaryRamSizePcd
+
+ xor eax, eax
+ mov ax, WORD [esi + 020h] ; Read ImageAttribute
+ test ax, 16 ; check if Bit4 is set
+ jnz ConsumeInputConfiguration
+ ;
+ ; Sometimes user may change input value even if it is not supported
+ ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.
+ ;
+ cmp ebx, edx
+ je UseTemporaryRamSizePcd
+ mov eax, 080000002h ; RETURN_INVALID_PARAMETER
+ jmp TempRamInitExit
+ConsumeInputConfiguration:
+ ;
+ ; Read Fsp Arch2 revision
+ ;
+ cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3
+ jb UseTemporaryRamSizePcd
+ ;
+ ; Read ARCH2 UPD value and Save.
+ ;
+ SAVE_TEMPORARY_RAM_SIZE ebx
+ jmp GotTemporaryRamSize
+UseTemporaryRamSizePcd:
+ SAVE_TEMPORARY_RAM_SIZE edx
+GotTemporaryRamSize:
+ LOAD_ECX
;
; Sec Platform Init
;
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
index 016f943b43..4d6ec1e984 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
@@ -128,6 +128,17 @@
SXMMN xmm5, 1, eax
%endmacro
+;
+; XMM5 slot 2 for TemporaryRamSize
+;
+%macro LOAD_TEMPORARY_RAM_SIZE 1
+ LXMMN xmm5, %1, 2
+ %endmacro
+
+%macro SAVE_TEMPORARY_RAM_SIZE 1
+ SXMMN xmm5, 2, %1
+ %endmacro
+
%macro ENABLE_SSE 0
;
; Initialize floating point units
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 11be1f97ca..8b41968760 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -47,7 +47,8 @@ FspGetExceptionHandler (
VOID
EFIAPI
SecGetPlatformData (
- IN OUT FSP_GLOBAL_DATA *FspData
+ IN OUT FSP_GLOBAL_DATA *FspData,
+ IN UINT32 TemporaryRamSize
)
{
FSP_PLAT_DATA *FspPlatformData;
@@ -68,10 +69,13 @@ SecGetPlatformData (
FspPlatformData->CodeRegionBase = 0;
FspPlatformData->CodeRegionSize = 0;
+ if (TemporaryRamSize == 0 || TemporaryRamSize == 0xFFFFFFFF) {
+ return;
+ }
//
// Pointer to the size field
//
- TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize);
+ TopOfCar = PcdGet32 (PcdTemporaryRamBase) + TemporaryRamSize;
StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32));
if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) {
@@ -123,7 +127,14 @@ FspGlobalDataInit (
VOID *FspmUpdDataPtr;
CHAR8 ImageId[9];
UINTN Idx;
+ UINTN *TopOfCar;
+ //
+ // If TempRam is initilized using FspTempRamInitApi (), GlobalDataPointer
+ // will point to the Top of the Car and any Data that FspTempRamInitApi
+ // wants to Handoff to later stages will be pushed on to the Top of the car.
+ //
+ TopOfCar = *(VOID **)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress);
//
// Set FSP Global Data pointer
//
@@ -147,7 +158,7 @@ FspGlobalDataInit (
// It may have multiple FVs, so look into the last one for FSP header
//
PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHeader ();
- SecGetPlatformData (PeiFspData);
+ SecGetPlatformData (PeiFspData, (UINTN)TopOfCar);
//
// Set API calling mode
diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index 5f59938518..33aaac66c1 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -42,9 +42,7 @@ FspApiCallingCheck (
//
// FspMemoryInit check
//
- if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData != MAX_UINT32)) {
- Status = EFI_UNSUPPORTED;
- } else if (ApiParam == NULL) {
+ if (ApiParam == NULL) {
Status = EFI_SUCCESS;
} else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
Status = EFI_INVALID_PARAMETER;
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index 698bb063a7..4a1da9f718 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -16,6 +16,7 @@
extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
+extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))
;
; Following functions will be provided in PlatformSecLib
@@ -76,7 +77,8 @@ struc LoadMicrocodeParamsFsp24
.FsptArchReserved: resb 3
.FsptArchLength: resd 1
.FspDebugHandler resq 1
- .FsptArchUpd: resd 4
+ .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is >= 3
+ .FsptArchUpd: resd 3
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resq 1
@@ -163,7 +165,7 @@ ASM_PFX(LoadMicrocodeDefault):
cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2
jb ParamError
cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2
- jne ParamError
+ jb ParamError
; UPD structure is compliant with FSP spec 2.4
mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
@@ -273,7 +275,7 @@ CheckAddress:
cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2
jb ParamError
cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2
- jne ParamError
+ jb ParamError
; UPD structure is compliant with FSP spec 2.4
; Is automatic size detection ?
@@ -337,9 +339,16 @@ ASM_PFX(EstablishStackFsp):
;
mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
mov esp, DWORD[rax]
- mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
- add esp, DWORD[rax]
-
+ LOAD_TEMPORARY_RAM_SIZE rax
+ add esp, eax
+ ;
+ ; Save top of the TemporaryRam in PcdGlobalDataPointerAddress
+ ; where the FspTempRamInitAPI information is pushed as part of below code
+ ; which will be used in other Fsp APIs to retrive the same.
+ ;
+ mov rax, ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))
+ mov eax, DWORD[rax]
+ mov DWORD[eax], esp
sub esp, 4
mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region
sub esp, 4
@@ -349,7 +358,7 @@ ASM_PFX(EstablishStackFsp):
cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2
jb ParamError1
cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2
- je Fsp24UpdHeader
+ jnb Fsp24UpdHeader
ParamError1:
mov rax, 08000000000000002h
@@ -397,8 +406,8 @@ ContinueAfterUpdPush:
;
mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
mov edx, [ecx]
- mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
- add edx, [ecx]
+ LOAD_TEMPORARY_RAM_SIZE rcx
+ add edx, ecx
mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
sub edx, [ecx]
mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
@@ -439,6 +448,14 @@ ASM_PFX(TempRamInitApi):
;
SAVE_BFV rbp
+ ;
+ ; Save timestamp into YMM6
+ ;
+ rdtsc
+ shl rdx, 32
+ or rax, rdx
+ SAVE_TS rax
+
;
; Save Input Parameter in YMM10
;
@@ -455,14 +472,47 @@ ASM_PFX(TempRamInitApi):
ParamValid:
SAVE_RCX
+ mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
+ mov edx, DWORD [rdx]
;
- ; Save timestamp into YMM6
+ ; Read ARCH2 UPD input value.
;
- rdtsc
- shl rdx, 32
- or rax, rdx
- SAVE_TS rax
+ mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize]
+ ;
+ ; As per spec, if Bootloader pass zero, use Fsp defined Size
+ ; Irrespective of whether this UPD is supported or not, Fallback
+ ; to Fsp defined size if input is zero.
+ ;
+ cmp ebx, 0
+ jz UseTemporaryRamSizePcd
+
+ xor rax, rax
+ mov ax, WORD [rsi + 020h] ; Read ImageAttribute
+ test ax, 16 ; check if Bit4 is set
+ jnz ConsumeInputConfiguration
+ ;
+ ; Sometimes user may change input value even if it is not supported
+ ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.
+ ;
+ cmp ebx, edx
+ je UseTemporaryRamSizePcd
+ mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER
+ jmp TempRamInitExit
+ConsumeInputConfiguration:
+ ;
+ ; Read Fsp Arch2 revision
+ cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3
+ jb UseTemporaryRamSizePcd
+ ;
+ ; Read ARCH2 UPD value and Save.
+ ; Only low-32 bits of rbx/rdx holds the temporary ram size.
+ ;
+ SAVE_TEMPORARY_RAM_SIZE rbx
+ jmp GotTemporaryRamSize
+UseTemporaryRamSizePcd:
+ SAVE_TEMPORARY_RAM_SIZE rdx
+GotTemporaryRamSize:
;
; Sec Platform Init
;
diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h
b/IntelFsp2Pkg/Include/FspEas/FspApi.h
index 40e063e944..27d5ec3a3c 100644
--- a/IntelFsp2Pkg/Include/FspEas/FspApi.h
+++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h
@@ -139,7 +139,7 @@ typedef struct {
///
typedef struct {
///
- /// Revision of the structure is 2 for this version of the specification.
+ /// Revision of the structure is 3 for this version of the specification.
///
UINT8 Revision;
UINT8 Reserved[3];
@@ -152,7 +152,8 @@ typedef struct {
/// occurring during FSP execution.
///
EFI_PHYSICAL_ADDRESS FspDebugHandler;
- UINT8 Reserved1[16];
+ UINT32 FspTemporaryRamSize;
+ UINT8 Reserved1[12];
} FSPT_ARCH2_UPD;
///
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index 002a5a1412..2168564e6d 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -201,6 +201,27 @@
movq rcx, xmm5
%endmacro
+;
+; Save TemporaryRamSize to YMM10[192:255]
+; arg 1:general purpose register which holds TemporaryRamSize
+; Modified: XMM5 and YMM10[192:255]
+;
+%macro SAVE_TEMPORARY_RAM_SIZE 1
+ LYMMN ymm10, xmm5, 1
+ SXMMN xmm5, 1, %1
+ SYMMN ymm10, 1, xmm5
+ %endmacro
+
+;
+; Restore TemporaryRamSize from YMM10[192:255]
+; arg 1:general purpose register where to save TemporaryRamSize
+; Modified: XMM5 and %1
+;
+%macro LOAD_TEMPORARY_RAM_SIZE 1
+ LYMMN ymm10, xmm5, 1
+ LXMMN xmm5, %1, 1
+ %endmacro
+
;
; YMM7[128:191] for calling stack
; arg 1:Entry
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index d1c3d3ee7b..426d31a13f 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -85,6 +85,11 @@
gFspEventEndOfFirmwareGuid = { 0xbd44f629, 0xeae7, 0x4198, {
0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
[PcdsFixedAtBuild]
+ #
+ # As part of FSP-T execution, this will be initialized to TemporaryRamSize
that FSP-T used
+ # for TemporaryRam configuraiton.Once Fsp Global Data is initialed later in
FSP-M, this
+ # will hold the Global data buffer address.
+ #
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
|0xFED00108|UINT32|0x00000001
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
|0xFEF00000|UINT32|0x10001001
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize |
0x2000|UINT32|0x10001002
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
index fb0d9a8683..316c2fa86a 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
@@ -49,8 +49,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA
FsptUpdDataPtr = {
},
0x00000020,
0x00000000,
+ 0x00000000,
{
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
},
--
2.39.1.windows.1
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