Hi Dat, Thanks for catching this corner case. The code change looks good to me.
Best Regards, Gao -----Original Message----- From: Wu, Hao A <hao.a...@intel.com> Sent: Monday, March 11, 2024 11:27 AM To: Dat Mach <dm...@nvidia.com>; gaoliming <gaolim...@byosoft.com.cn>; devel@edk2.groups.io Cc: Cheng, Gao <gao.ch...@intel.com>; Ni, Ray <ray...@intel.com> Subject: RE: [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB address translation No additional comment from my side. Best Regards, Hao Wu > -----Original Message----- > From: Dat Mach <dm...@nvidia.com> > Sent: Saturday, March 9, 2024 7:33 AM > To: gaoliming <gaolim...@byosoft.com.cn>; devel@edk2.groups.io > Cc: Cheng, Gao <gao.ch...@intel.com>; Wu, Hao A <hao.a...@intel.com>; > Ni, Ray <ray...@intel.com> > Subject: RE: [PATCH] MdeModulePkg/Xhci: Skip another size round up for > TRB address translation > > Hi Gao and Hao, > > Could you please take a look at my patch and see if anything I might > have missed? > > Thanks, > Dat > > -----Original Message----- > From: gaoliming <gaolim...@byosoft.com.cn> > Sent: Monday, March 4, 2024 4:34 PM > To: Dat Mach <dm...@nvidia.com>; devel@edk2.groups.io > Cc: gao.ch...@intel.com; hao.a...@intel.com; ray...@intel.com > Subject: 回复: [PATCH] MdeModulePkg/Xhci: Skip another size round up for > TRB address translation > > External email: Use caution opening links or attachments > > > This change looks good. Reviewed-by: Liming Gao > <gaolim...@byosoft.com.cn> > > Cheng and Hao: > Have you any comments for this patch? > > Thanks > Liming > > -----邮件原件----- > > 发件人: Dat Mach <dm...@nvidia.com> > > 发送时间: 2024年2月26日 10:00 > > 收件人: devel@edk2.groups.io > > 抄送: gao.ch...@intel.com; hao.a...@intel.com; ray...@intel.com; > > gaolim...@byosoft.com.cn; Dat Mach <dm...@nvidia.com> > > 主题: [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB > > address translation > > > > REF:https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F% > > 2F > > > bugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D4560&data=05%7C02%7Cd > mach > > %40nvidia.com%7C135326cf31634dbe703e08dc3cac0417%7C43083d1572 > 7340c1b7d > > > b39efd9ccc17a%7C0%7C0%7C638451956723393894%7CUnknown%7CTWFp > bGZsb3d8eyJ > > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > 7C0%7C > > %7C%7C&sdata=JlpbOr0QHodUF7QDJZl5gY88maLemat4ktudCyDShMQ%3D > &reserved=0 > > > > Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the > > DXE_ASSERT caused by the TRB size round up from 16 to 64 for most > > cases. > > > > However, there is a remaining case that the TRB size is also rounded > > up during setting TR dequeue pointer that would trigger DXE_ASSERT. > > > > This patch sets the alignment flag to FALSE in > > XhcSetTrDequeuePointer to fix this issue as well. > > > > Signed-off-by: Dat Mach <dm...@nvidia.com> > > --- > > MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 2 +- > > MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > index 05528a478b..5d735008ba 100644 > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > @@ -3539,7 +3539,7 @@ XhcSetTrDequeuePointer ( > > // Send stop endpoint command to transit Endpoint from running to > > stop state > > // > > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); > > - PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); > > + PhyAddr = UsbHcGetPciAddrForHostAddr > > (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof > > (CMD_SET_TR_DEQ_POINTER), FALSE); > > CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | > > Urb->Ring->RingPCS; > > CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr); > > CmdSetTRDeq.CycleBit = 1; > > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > index 53272f62dd..c956e45907 100644 > > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > @@ -2526,7 +2526,7 @@ XhcPeiSetTrDequeuePointer ( > > // Send stop endpoint command to transit Endpoint from running to > > stop state > > // > > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); > > - PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); > > + PhyAddr = UsbHcGetPciAddrForHostAddr > > (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof > > (CMD_SET_TR_DEQ_POINTER), FALSE); > > CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | > > Urb->Ring->RingPCS; > > CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr); > > CmdSetTRDeq.CycleBit = 1; > > -- > > 2.44.0.rc2 > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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