Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com> > -----Original Message----- > From: Hsueh, DoraX <dorax.hs...@intel.com> > Sent: Monday, March 25, 2024 10:48 PM > To: devel@edk2.groups.io > Cc: Hsueh, DoraX <dorax.hs...@intel.com>; Chaganty, Rangasai V > <rangasai.v.chaga...@intel.com>; Chuang, Rosen <rosen.chu...@intel.com>; > Kasbekar, Saloni <saloni.kasbe...@intel.com>; Tang, Haoyu > <haoyu.t...@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desim...@intel.com> > Subject: [PATCH] AlderlakeOpenBoardPkg: Change MinPlatform MinDsdt and > Update SpiFlashCommonLib > > From: DoraX Hsueh <dorax.hs...@intel.com> > > https://bugzilla.tianocore.org/show_bug.cgi?id=4662 > > 1. Change MinPlatform MinDsdt to fix hang logo issue. > 2. Update SecFspWrapperPlatformSecLib for FSP use. > 3. Update SpiFlashCommonLib to fix boot assert issue. > 4. Create SmmLocked callback to fix assert > > Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> > Cc: Rosen Chuang <rosen.chu...@intel.com> > Cc: Saloni Kasbekar <saloni.kasbe...@intel.com> > Cc: Haoyu Tang <haoyu.t...@intel.com> > Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> > Signed-off-by: DoraX Hsueh <dorax.hs...@intel.com> > --- > .../Acpi/MinDsdt/MinDsdt.asl | 68 --- > .../Acpi/MinDsdt/MinDsdt.c | 232 ----------- > .../Acpi/MinDsdt/MinDsdt.inf | 48 --- > .../AlderlakePRvp/OpenBoardPkg.dsc | 6 +- > .../AlderlakePRvp/OpenBoardPkg.fdf | 2 +- > .../AlderlakePRvp/OpenBoardPkgPcd.dsc | 8 + > .../FspWrapperPlatformSecLib.c | 186 +++++++++ > .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 394 ++++++++++++++++++ > .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 ++ > .../Ia32/PeiCoreEntry.nasm | 130 ++++++ > .../Ia32/SecEntry.nasm | 361 ++++++++++++++++ > .../Ia32/Stack.nasm | 72 ++++ > .../PlatformInit.c | 47 +++ > .../SecFspWrapperPlatformSecLib.inf | 106 +++++ > .../SecGetPerformance.c | 89 ++++ > .../SecPlatformInformation.c | 78 ++++ > .../SecRamInitData.c | 57 +++ > .../SecTempRamDone.c | 93 +++++ > .../Include/Library/SpiFlashCommon.h | 99 ----- > .../SmmSpiFlashCommonLib.inf | 49 --- > .../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ---------- > .../SpiFlashCommonSmmLib.c | 60 --- > .../OpenBoardPlatformInitPostMem.c | 96 +---- > .../OpenBoardPlatformInitPostMem.inf | 20 - > .../DxeSaPolicyInit.c | 71 ++++ > .../DxeSiliconPolicyUpdateLib.inf | 2 + > .../PeiCpuPolicyUpdatePreMem.c | 3 - > .../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 3 +- > 28 files changed, 1742 insertions(+), 895 deletions(-) > delete mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl > delete mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c > delete mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c > create mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c > delete mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h > delete mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf > delete mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c > delete mode 100644 > Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c > > diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl > b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl > deleted file mode 100644 > index be110145..00000000 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl > +++ /dev/null > @@ -1,68 +0,0 @@ > -/** @file > - ACPI minimum DSDT table > - > - Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > -**/ > - > -DefinitionBlock ( > - "DSDT.aml", > - "DSDT", > - 0x01, // DSDT revision. > - // A Revision field value greater than or equal to 2 signifies that > integers > - // declared within the Definition Block are to be evaluated as > 64-bit values > - "INTEL ", // OEM ID (6 byte string) > - "MIN ",// OEM table ID (8 byte string) > - 0x00 // OEM version of DSDT table (4 byte Integer) > -) > - > -// BEGIN OF ASL SCOPE > -{ > - Scope(\_SB) { > - > //--------------------------------------------------------------------------- > - // Begin PCI tree object scope > - > //--------------------------------------------------------------------------- > - Device(PCI0) { // PCI Bridge "Host Bridge" > - Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 > host hierarchy > - Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't > understand the new HID > - Name(_SEG, 0) > - Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for > Peer PCI busses. Name can be overriden with control method placed directly > under Device scope > - Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root > PCI Bus > - Name(_UID, 0x0000) // Unique Bus ID, optional > - Name(BUF0,ResourceTemplate() > - { > - // > - // PCI Configuration Registers ( 0x0CF8 - 0x0CFF ) > - // > - Io(Decode16,0x0CF8,0x0CF8,1,0x08) > - // > - // PCI MMIO space > - // > - > DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, > - ReadWrite,0x00,0x00,0x00,0x00,0x00,,,PM01) > - }) > - Method(_CRS,0,Serialized) > - { > - // > - // Create pointers to Memory Sizing values. > - // > - CreateDwordField(BUF0, ^PM01._MIN,M1MN) > - CreateDwordField(BUF0, ^PM01._MAX,M1MX) > - CreateDwordField(BUF0, ^PM01._LEN,M1LN) > - > - // > - // Set Memory Size Values. TLUD represents bits 31:20 of phyical > - // TOM, so shift these bits into the correct position and fix up > - // the Memory Region available to PCI. > - // > - Subtract > (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase),M1LN) > - Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN) > - Subtract (FixedPcdGet32(PcdPciReservedMemLimit), 1, M1MX) > - > - Return(BUF0) > - } > - } > - } > -}// End of ASL File > - > diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c > b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c > deleted file mode 100644 > index 08709a43..00000000 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c > +++ /dev/null > @@ -1,232 +0,0 @@ > -/** @file > - Min DSDT Driver > - > - Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > -**/ > - > -#include <Base.h> > -#include <Uefi.h> > -#include <IndustryStandard/Acpi.h> > -#include <Library/UefiLib.h> > -#include <Library/UefiBootServicesTableLib.h> > -#include <Library/UefiRuntimeServicesTableLib.h> > -#include <Library/DebugLib.h> > -#include <Library/BaseMemoryLib.h> > -#include <Library/IoLib.h> > -#include <Library/PcdLib.h> > -#include <Library/PciLib.h> > -#include <Library/MemoryAllocationLib.h> > - > -#include <Protocol/FirmwareVolume2.h> > -#include <Protocol/AcpiTable.h> > - > -// > -// Function implementations > -// > - > -/** > - Locate the first instance of a protocol. If the protocol requested is an > - FV protocol, then it will return the first FV that contains the ACPI table > - storage file. > - > - @param[in] Protocol The protocol to find. > - @param[in] FfsGuid The FFS that contains the ACPI table. > - @param[out] Instance Return pointer to the first instance of the > protocol. > - > - @retval EFI_SUCCESS The function completed successfully. > - @retval EFI_NOT_FOUND The protocol could not be located. > - @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the > protocol. > -**/ > -EFI_STATUS > -LocateSupportProtocol ( > - IN EFI_GUID *Protocol, > - IN EFI_GUID *FfsGuid, > - OUT VOID **Instance > - ) > -{ > - EFI_STATUS Status; > - EFI_HANDLE *HandleBuffer; > - UINTN NumberOfHandles; > - EFI_FV_FILETYPE FileType; > - UINT32 FvStatus; > - EFI_FV_FILE_ATTRIBUTES Attributes; > - UINTN Size; > - UINTN Index; > - > - // > - // Locate protocol. > - // > - Status = gBS->LocateHandleBuffer ( > - ByProtocol, > - Protocol, > - NULL, > - &NumberOfHandles, > - &HandleBuffer > - ); > - if (EFI_ERROR (Status)) { > - // > - // Defined errors at this time are not found and out of resources. > - // > - return Status; > - } > - > - // > - // Looking for FV with ACPI storage file > - // > - for (Index = 0; Index < NumberOfHandles; Index++) { > - > - // > - // Get the protocol on this handle > - // This should not fail because of LocateHandleBuffer > - // > - Status = gBS->HandleProtocol ( > - HandleBuffer[Index], > - Protocol, > - Instance > - ); > - ASSERT_EFI_ERROR (Status); > - > - // > - // See if it has the ACPI storage file > - // > - Size = 0; > - FvStatus = 0; > - Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile ( > - *Instance, > - FfsGuid, > - NULL, > - &Size, > - &FileType, > - &Attributes, > - &FvStatus > - ); > - > - // > - // If we found it, then we are done > - // > - if (Status == EFI_SUCCESS) { > - break; > - } > - } > - > - // > - // Our exit status is determined by the success of the previous operations > - // If the protocol was found, Instance already points to it. > - // > - // > - // Free any allocated buffers > - // > - FreePool (HandleBuffer); > - > - return Status; > -} > - > -/** > - Publish ACPI table from FV. > - > - @param[in] FfsGuid The FFS that contains the ACPI table. > - > - @retval EFI_SUCCESS The function completed successfully. > -**/ > -EFI_STATUS > -PublishAcpiTablesFromFv ( > - IN EFI_GUID *FfsGuid > - ) > -{ > - EFI_STATUS Status; > - EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; > - EFI_ACPI_COMMON_HEADER *CurrentTable; > - UINT32 FvStatus; > - UINTN Size; > - UINTN TableHandle; > - INTN Instance; > - EFI_ACPI_TABLE_PROTOCOL *AcpiTable; > - > - Instance = 0; > - TableHandle = 0; > - CurrentTable = NULL; > - FwVol = NULL; > - > - Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID > **)&AcpiTable); > - ASSERT_EFI_ERROR (Status); > - > - // > - // Locate the firmware volume protocol > - // > - Status = LocateSupportProtocol ( > - &gEfiFirmwareVolume2ProtocolGuid, > - FfsGuid, > - (VOID **) &FwVol > - ); > - ASSERT_EFI_ERROR (Status); > - > - // > - // Read tables from the storage file. > - // > - > - while (Status == EFI_SUCCESS) { > - Status = FwVol->ReadSection ( > - FwVol, > - FfsGuid, > - EFI_SECTION_RAW, > - Instance, > - (VOID **) &CurrentTable, > - &Size, > - &FvStatus > - ); > - > - if (!EFI_ERROR (Status)) { > - > - // > - // Add the table > - // > - TableHandle = 0; > - Status = AcpiTable->InstallAcpiTable ( > - AcpiTable, > - CurrentTable, > - CurrentTable->Length, > - &TableHandle > - ); > - ASSERT_EFI_ERROR (Status); > - > - // > - // Increment the instance > - // > - Instance++; > - CurrentTable = NULL; > - } > - } > - > - // > - // Finished > - // > - return EFI_SUCCESS; > -} > - > -/** > - ACPI Platform driver installation function. > - > - @param[in] ImageHandle Handle for this drivers loaded image protocol. > - @param[in] SystemTable EFI system table. > - > - @retval EFI_SUCCESS The driver installed without error. > - @retval EFI_ABORTED The driver encountered an error and could not > complete installation of > - the ACPI tables. > - > -**/ > -EFI_STATUS > -EFIAPI > -InstallMinDsdt ( > - IN EFI_HANDLE ImageHandle, > - IN EFI_SYSTEM_TABLE *SystemTable > - ) > -{ > - EFI_STATUS Status; > - > - Status = PublishAcpiTablesFromFv (&gEfiCallerIdGuid); > - ASSERT_EFI_ERROR (Status); > - > - return EFI_SUCCESS; > -} > diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf > b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf > deleted file mode 100644 > index f2571407..00000000 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf > +++ /dev/null > @@ -1,48 +0,0 @@ > -### @file > -# Component information file for Minimal DSDT module > -# > -# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > -# SPDX-License-Identifier: BSD-2-Clause-Patent > -# > -# > -# @par Glossary: > -### > - > -[Defines] > - INF_VERSION = 0x00010005 > - BASE_NAME = MinDsdt > - FILE_GUID = 8EB04370-482C-4505-AA27-7EB226A5729F > - MODULE_TYPE = DXE_DRIVER > - VERSION_STRING = 1.0 > - ENTRY_POINT = InstallMinDsdt > - > -[Sources.common] > - MinDsdt.c > - MinDsdt.asl > - > -[Packages] > - MdePkg/MdePkg.dec > - MinPlatformPkg/MinPlatformPkg.dec > - > -[LibraryClasses] > - UefiDriverEntryPoint > - BaseLib > - DebugLib > - PcdLib > - UefiBootServicesTableLib > - UefiRuntimeServicesTableLib > - BaseMemoryLib > - MemoryAllocationLib > - > -[Protocols] > - gEfiAcpiTableProtocolGuid ## CONSUMES > - gEfiFirmwareVolume2ProtocolGuid ## CONSUMES > - > -[Pcd] > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit > - > -[Depex] > - gEfiAcpiTableProtocolGuid AND > - gEfiFirmwareVolume2ProtocolGuid > - > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc > b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc > index 4cdc9c01..59350f06 100644 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc > +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc > @@ -101,7 +101,7 @@ > > > PostCodeMapLib|PostCodeDebugFeaturePkg/Library/PostCodeMapLib/PostCodeMapLib.inf > > - > PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > + > PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf > > FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf > > @@ -234,7 +234,7 @@ > [LibraryClasses.X64.DXE_SMM_DRIVER] > > !if $(TARGET) == DEBUG > - > SpiFlashCommonLib|$(PLATFORM_BOARD_PACKAGE)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf > + > SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf > > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf > > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf > !endif > @@ -453,7 +453,7 @@ $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf > # > !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE > $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf > - $(PLATFORM_BOARD_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf > + $(PLATFORM_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf > $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { > <LibraryClasses> > NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf > b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf > index f1ce271b..27366fc4 100644 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf > +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf > @@ -485,7 +485,7 @@ APRIORI DXE { > !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE > INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf > -INF RuleOverride = DRIVER_ACPITABLE > $(PLATFORM_BOARD_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf > +INF RuleOverride = DRIVER_ACPITABLE > $(PLATFORM_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf > INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf > > !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc > b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc > index 3eb9a575..edcd33e6 100644 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc > +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc > @@ -174,6 +174,13 @@ > gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > !endif > > + # > + # INIT is now triggered before BIOS by ucode/hardware. In the OVMF > + # environment, QEMU lacks a simulation for the INIT process. > + # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to > + # broadcast INIT-SIPI-SIPI for the first time. > + # > + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE > > !if $(TARGET) == DEBUG > !if gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable == TRUE > @@ -287,6 +294,7 @@ > > > [PcdsDynamicDefault] > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020204C4349 > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c > new file mode 100644 > index 00000000..d6796be5 > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c > @@ -0,0 +1,186 @@ > +/** @file > + Provide FSP wrapper platform sec related function. > + > +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include <PiPei.h> > + > +#include <Ppi/SecPlatformInformation.h> > +#include <Ppi/SecPerformance.h> > +#include <Ppi/FirmwareVolumeInfo.h> > +#include <Ppi/TopOfTemporaryRam.h> > +#include <Ppi/PeiCoreFvLocation.h> > +#include <Guid/FirmwareFileSystem2.h> > + > +#include <Library/LocalApicLib.h> > +#include <Library/BaseMemoryLib.h> > +#include <Library/DebugLib.h> > +#include <Library/IoLib.h> > + > +/** > + This interface conveys state information out of the Security (SEC) phase > into PEI. > + > + @param[in] PeiServices Pointer to the PEI Services Table. > + @param[in,out] StructureSize Pointer to the variable > describing size of the input buffer. > + @param[out] PlatformInformationRecord Pointer to the > EFI_SEC_PLATFORM_INFORMATION_RECORD. > + > + @retval EFI_SUCCESS The data was successfully returned. > + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecPlatformInformation ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN OUT UINT64 *StructureSize, > + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord > + ); > + > +/** > + This interface conveys performance information out of the Security (SEC) > phase into PEI. > + > + This service is published by the SEC phase. The SEC phase handoff has an > optional > + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed > from SEC into the > + PEI Foundation. As such, if the platform supports collecting performance > data in SEC, > + this information is encapsulated into the data structure abstracted by > this service. > + This information is collected for the boot-strap processor (BSP) on IA-32. > + > + @param[in] PeiServices The pointer to the PEI Services Table. > + @param[in] This The pointer to this instance of the > PEI_SEC_PERFORMANCE_PPI. > + @param[out] Performance The pointer to performance data collected in SEC > phase. > + > + @retval EFI_SUCCESS The data was successfully returned. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecGetPerformance ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN PEI_SEC_PERFORMANCE_PPI *This, > + OUT FIRMWARE_SEC_PERFORMANCE *Performance > + ); > + > +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = { > + SecGetPerformance > +}; > + > +EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = { > + (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress) > +}; > + > +EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = { > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gEfiPeiCoreFvLocationPpiGuid, > + &mPeiCoreFvLocationPpi > + } > +}; > + > +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = { > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gTopOfTemporaryRamPpiGuid, > + NULL // To be patched later. > + }, > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, > + &gPeiSecPerformancePpiGuid, > + &mSecPerformancePpi > + }, > +}; > + > +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21 > +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1 > +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0 > +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1 > + > +/** > + Write to mask and edge/level triggered registers of master and slave 8259 > PICs. > + > + @param[in] Mask low byte for master PIC mask register, > + high byte for slave PIC mask register. > + @param[in] EdgeLevel low byte for master PIC edge/level triggered > register, > + high byte for slave PIC edge/level triggered > register. > + > +**/ > +VOID > +Interrupt8259WriteMask ( > + IN UINT16 Mask, > + IN UINT16 EdgeLevel > + ) > +{ > + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask); > + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8)); > + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) > EdgeLevel); > + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) > (EdgeLevel >> 8)); > +} > + > +/** > + A developer supplied function to perform platform specific operations. > + > + It's a developer supplied function to perform any operations appropriate > to a > + given platform. It's invoked just before passing control to PEI core by SEC > + core. Platform developer may modify the SecCoreData passed to PEI Core. > + It returns a platform specific PPI list that platform wishes to pass to > PEI core. > + The Generic SEC core module will merge this list to join the final list > passed to > + PEI core. > + > + @param[in,out] SecCoreData The same parameter as passing to PEI > core. It > + could be overridden by this function. > + > + @return The platform specific PPI list to be passed to PEI core or > + NULL if there is no need of such platform specific PPI list. > + > +**/ > +EFI_PEI_PPI_DESCRIPTOR * > +EFIAPI > +SecPlatformMain ( > + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData > + ) > +{ > + EFI_PEI_PPI_DESCRIPTOR *PpiList; > + UINT8 TopOfTemporaryRamPpiIndex; > + UINT8 *CopyDestinationPointer; > + > + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", > SecCoreData->BootFirmwareVolumeBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", > SecCoreData->BootFirmwareVolumeSize)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", > SecCoreData->TemporaryRamBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", > SecCoreData->TemporaryRamSize)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", > SecCoreData->PeiTemporaryRamBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", > SecCoreData->PeiTemporaryRamSize)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", > SecCoreData->StackBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", > SecCoreData->StackSize)); > + > + InitializeApicTimer (0, (UINT32) -1, TRUE, 5); > + > + // > + // Set all 8259 interrupts to edge triggered and disabled > + // > + Interrupt8259WriteMask (0xFFFF, 0x0000); > + > + // > + // Use middle of Heap as temp buffer, it will be copied by caller. > + // Do not use Stack, because it will cause wrong calculation on stack by > PeiCore > + // > + PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) > SecCoreData->PeiTemporaryRamSize/2); > + CopyDestinationPointer = (UINT8 *) PpiList; > + TopOfTemporaryRamPpiIndex = 0; > + if ((PcdGet8 (PcdFspModeSelection) == 0) && PcdGetBool > (PcdFspDispatchModeUseFspPeiMain)) { > + // > + // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi. > + // > + CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof > (mPeiCoreFvLocationPpiList)); > + TopOfTemporaryRamPpiIndex = 1; > + CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList); > + } > + CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof > (mPeiSecPlatformPpi)); > + // > + // Patch TopOfTemporaryRamPpi > + // > + PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) > SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize); > + > + return PpiList; > +} > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h > new file mode 100644 > index 00000000..f92ed50e > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h > @@ -0,0 +1,394 @@ > +/** @file > + > +Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef __FSPT_CORE_UPD_H__ > +#define __FSPT_CORE_UPD_H__ > + > +#include <FspUpd.h> > + > +#pragma pack(1) > + > +/** Fsp T Core UPD > +**/ > +typedef struct { > + > +/** Offset 0x0020 > +**/ > + UINT32 MicrocodeRegionBase; > + > +/** Offset 0x0024 > +**/ > + UINT32 MicrocodeRegionSize; > + > +/** Offset 0x0028 > +**/ > + UINT32 CodeRegionBase; > + > +/** Offset 0x002C > +**/ > + UINT32 CodeRegionSize; > + > +/** Offset 0x0030 > +**/ > + UINT8 Reserved[16]; > +} FSPT_CORE_UPD; > + > +/** Fsp T Configuration > +**/ > +typedef struct { > + > +/** Offset 0x0060 - PcdSerialIoUartDebugEnable > + Enable SerialIo Uart debug library with/without initializing SerialIo Uart > device in FSP. > + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing > +**/ > + UINT8 PcdSerialIoUartDebugEnable; > + > +/** Offset 0x0061 - PcdSerialIoUartNumber > + Select SerialIo Uart Controller for debug. > + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 > +**/ > + UINT8 PcdSerialIoUartNumber; > + > +/** Offset 0x0062 - PcdSerialIoUartMode - FSPT > + Select SerialIo Uart Controller mode > + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, > 3:SerialIoUartCom, > + 4:SerialIoUartSkipInit > +**/ > + UINT8 PcdSerialIoUartMode; > + > +/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT > + Select SerialIo Uart Controller Powergating mode > + 0:Disabled, 1:Enabled, 2:Auto > +**/ > + UINT8 PcdSerialIoUartPowerGating; > + > +/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT > + Set default BaudRate Supported from 0 - default to 6000000 > +**/ > + UINT32 PcdSerialIoUartBaudRate; > + > +/** Offset 0x0068 - Pci Express Base Address > + Base address to be programmed for Pci Express > +**/ > + UINT64 PcdPciExpressBaseAddress; > + > +/** Offset 0x0070 - Pci Express Region Length > + Region Length to be programmed for Pci Express > +**/ > + UINT32 PcdPciExpressRegionLength; > + > +/** Offset 0x0074 - PcdSerialIoUartParity - FSPT > + Set default Parity. > + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity > +**/ > + UINT8 PcdSerialIoUartParity; > + > +/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT > + Set default word length. 0: Default, 5,6,7,8 > +**/ > + UINT8 PcdSerialIoUartDataBits; > + > +/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT > + Set default stop bits. > + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits > +**/ > + UINT8 PcdSerialIoUartStopBits; > + > +/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT > + Enables UART hardware flow control, CTS and RTS lines. > + 0: Disable, 1:Enable > +**/ > + UINT8 PcdSerialIoUartAutoFlow; > + > +/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT > + Select RX pin muxing for SerialIo UART used for debug > +**/ > + UINT32 PcdSerialIoUartRxPinMux; > + > +/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT > + Select TX pin muxing for SerialIo UART used for debug > +**/ > + UINT32 PcdSerialIoUartTxPinMux; > + > +/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT > + Select SerialIo Uart used for debug Rts pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_RTS* > + for possible values. > +**/ > + UINT32 PcdSerialIoUartRtsPinMux; > + > +/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT > + Select SerialIo Uart used for debug Cts pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_CTS* > + for possible values. > +**/ > + UINT32 PcdSerialIoUartCtsPinMux; > + > +/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT > + Select SerialIo Uart default MMIO resource in SEC/PEI phase when > PcdSerialIoUartMode > + = SerialIoUartPci. > +**/ > + UINT32 PcdSerialIoUartDebugMmioBase; > + > +/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT > + Specify PciCfgBase address. Allows for SerialIO UART functionality outside > Bus 0 > +**/ > + UINT32 PcdSerialIoUartDebugPciCfgBase; > + > +/** Offset 0x0090 - PcdLpcUartDebugEnable > + Enable to initialize LPC Uart device in FSP. > + 0:Disable, 1:Enable > +**/ > + UINT8 PcdLpcUartDebugEnable; > + > +/** Offset 0x0091 - Debug Interfaces > + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, > BIT5-TraceHub, > + BIT2 - Not used. > +**/ > + UINT8 PcdDebugInterfaceFlags; > + > +/** Offset 0x0092 - PcdSerialDebugLevel > + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, > 3:Load, > + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, > Error, Warnings, > + Info & Verbose. > + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and > Info, 4:Load > + Error Warnings and Info, 5:Load Error Warnings Info and Verbose > +**/ > + UINT8 PcdSerialDebugLevel; > + > +/** Offset 0x0093 - ISA Serial Base selection > + Select ISA Serial Base address. Default is 0x3F8. > + 0:0x3F8, 1:0x2F8 > +**/ > + UINT8 PcdIsaSerialUartBase; > + > +/** Offset 0x0094 - PcdSerialIo2ndUartEnable > + Enable Additional SerialIo Uart device in FSP. > + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing > +**/ > + UINT8 PcdSerialIo2ndUartEnable; > + > +/** Offset 0x0095 - PcdSerialIo2ndUartNumber > + Select SerialIo Uart Controller Number > + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 > +**/ > + UINT8 PcdSerialIo2ndUartNumber; > + > +/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT > + Select SerialIo Uart Controller mode > + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, > 3:SerialIoUartCom, > + 4:SerialIoUartSkipInit > +**/ > + UINT8 PcdSerialIo2ndUartMode; > + > +/** Offset 0x0097 > +**/ > + UINT8 Rsvd020[1]; > + > +/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT > + Set default BaudRate Supported from 0 - default to 6000000 > +**/ > + UINT32 PcdSerialIo2ndUartBaudRate; > + > +/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT > + Set default Parity. > + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity > +**/ > + UINT8 PcdSerialIo2ndUartParity; > + > +/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT > + Set default word length. 0: Default, 5,6,7,8 > +**/ > + UINT8 PcdSerialIo2ndUartDataBits; > + > +/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT > + Set default stop bits. > + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits > +**/ > + UINT8 PcdSerialIo2ndUartStopBits; > + > +/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT > + Enables UART hardware flow control, CTS and RTS lines. > + 0: Disable, 1:Enable > +**/ > + UINT8 PcdSerialIo2ndUartAutoFlow; > + > +/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT > + Select RX pin muxing for SerialIo UART > +**/ > + UINT32 PcdSerialIo2ndUartRxPinMux; > + > +/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT > + Select TX pin muxing for SerialIo UART > +**/ > + UINT32 PcdSerialIo2ndUartTxPinMux; > + > +/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT > + Select SerialIo Uart Rts pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_RTS* > + for possible values. > +**/ > + UINT32 PcdSerialIo2ndUartRtsPinMux; > + > +/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT > + Select SerialIo Uart Cts pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_UARTx_CTS* > + for possible values. > +**/ > + UINT32 PcdSerialIo2ndUartCtsPinMux; > + > +/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT > + Select SerialIo Uart default MMIO resource in SEC/PEI phase when > PcdSerialIo2ndUartMode > + = SerialIoUartPci. > +**/ > + UINT32 PcdSerialIo2ndUartMmioBase; > + > +/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT > + Specify PciCfgBase address. Allows for SerialIO UART functionality outside > Bus 0 > +**/ > + UINT32 PcdSerialIo2ndUartPciCfgBase; > + > +/** Offset 0x00B8 > +**/ > + UINT32 TopMemoryCacheSize; > + > +/** Offset 0x00BC - FspDebugHandler > + <b>Optional</b> pointer to the boot loader's implementation of > FSP_DEBUG_HANDLER. > +**/ > + UINT32 FspDebugHandler; > + > +/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity > + Sets polarity for each chip Select. Available options: > 0:SerialIoSpiCsActiveLow, > + 1:SerialIoSpiCsActiveHigh > +**/ > + UINT8 PcdSerialIoSpiCsPolarity[2]; > + > +/** Offset 0x00C2 - Serial Io SPI Chip Select Enable > + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled > +**/ > + UINT8 PcdSerialIoSpiCsEnable[2]; > + > +/** Offset 0x00C4 - Serial Io SPI Device Mode > + When mode is set to Pci, controller is initalized in early stage. > Available modes: > + 0:SerialIoSpiDisabled, 1:SerialIoSpiPci. > +**/ > + UINT8 PcdSerialIoSpiMode; > + > +/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output > + Sets Default CS as Output. Available options: 0:CS0, 1:CS1 > +**/ > + UINT8 PcdSerialIoSpiDefaultCsOutput; > + > +/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW > + Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW > +**/ > + UINT8 PcdSerialIoSpiCsMode; > + > +/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High > + Sets Default CS State Low or High. Available options: 0:Low, 1:High > +**/ > + UINT8 PcdSerialIoSpiCsState; > + > +/** Offset 0x00C8 - Serial Io SPI Device Number > + Select which Serial Io SPI controller is initalized in early stage. > +**/ > + UINT8 PcdSerialIoSpiNumber; > + > +/** Offset 0x00C9 > +**/ > + UINT8 Rsvd030[3]; > + > +/** Offset 0x00CC - Serial Io SPI Device MMIO Base > + Assigns MMIO for Serial Io SPI controller usage in early stage. > +**/ > + UINT32 PcdSerialIoSpiMmioBase; > + > +/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing > + Select SerialIo SPI CS pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_SPIx_CS* for > + possible values. > +**/ > + UINT32 PcdSerialIoSpiCsPinMux[2]; > + > +/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing > + Select SerialIo SPI CLK pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_SPIx_CLK* for > + possible values. > +**/ > + UINT32 PcdSerialIoSpiClkPinMux; > + > +/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing > + Select SerialIo SPI MISO pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_SPIx_MISO* > + for possible values. > +**/ > + UINT32 PcdSerialIoSpiMisoPinMux; > + > +/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing > + Select SerialIo SPI MOSI pin muxing. Refer to > GPIO_*_MUXING_SERIALIO_SPIx_MOSI* > + for possible values. > +**/ > + UINT32 PcdSerialIoSpiMosiPinMux; > + > +/** Offset 0x00E4 - Serial Io I2C Device MMIO Base > + Assigns MMIO for Serial Io I2C controller usage in early stage. > +**/ > + UINT32 PcdSerialIoI2cMmioBase; > + > +/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin > + Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for > possible values. > +**/ > + UINT32 PcdSerialIoI2cSdaPin; > + > +/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin > + Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for > possible values. > +**/ > + UINT32 PcdSerialIoI2cSclPin; > + > +/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination > + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm > weak pull-up, > + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads > termination > + respectively. One byte for each controller, byte0 for I2C0, byte1 for > I2C1, and so on. > +**/ > + UINT8 PcdSerialIoI2cPadsTerm; > + > +/** Offset 0x00F1 - Serial Io I2c Controller Number > + Select SerialIo I2C Controller number to be intilizaed during early boot. > Default is 0xFF > + 0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable > +**/ > + UINT8 PcdSerialIoI2cNumber; > + > +/** Offset 0x00F2 > +**/ > + UINT8 ReservedFsptUpd1[6]; > +} FSP_T_CONFIG; > + > +/** Fsp T UPD Configuration > +**/ > +typedef struct { > + > +/** Offset 0x0000 > +**/ > + FSP_UPD_HEADER FspUpdHeader; > + > +/** Offset 0x0020 > +**/ > + FSPT_ARCH_UPD FsptArchUpd; > + > +/** Offset 0x0040 > +**/ > + FSPT_CORE_UPD FsptCoreUpd; > + > +/** Offset 0x0060 > +**/ > + FSP_T_CONFIG FsptConfig; > + > +/** Offset 0x00F8 > +**/ > + UINT8 Rsvd3[6]; > + > +/** Offset 0x00FE > +**/ > + UINT16 UpdTerminator; > +} FSPT_UPD; > + > +#pragma pack() > + > +#endif > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h > new file mode 100644 > index 00000000..b8b5af6a > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h > @@ -0,0 +1,42 @@ > +/** @file > + Fsp related definitions > + > +Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef __FSP_H__ > +#define __FSP_H__ > + > +// > +// Fv Header > +// > +#define FVH_SIGINATURE_OFFSET 0x28 > +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH > +#define FVH_HEADER_LENGTH_OFFSET 0x30 > +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34 > +#define FVH_EXTHEADER_SIZE_OFFSET 0x10 > + > +// > +// Ffs Header > +// > +#define FSP_HEADER_GUID_DWORD1 0x912740BE > +#define FSP_HEADER_GUID_DWORD2 0x47342284 > +#define FSP_HEADER_GUID_DWORD3 0xB08471B9 > +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527 > +#define FFS_HEADER_SIZE_VALUE 0x18 > + > +// > +// Section Header > +// > +#define SECTION_HEADER_TYPE_OFFSET 0x03 > +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04 > + > +// > +// Fsp Header > +// > +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C > +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 > + > +#endif > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm > new file mode 100644 > index 00000000..1b6f0e2d > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm > @@ -0,0 +1,130 @@ > +;------------------------------------------------------------------------------ > +; > +; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> > +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; > +; Module Name: > +; > +; PeiCoreEntry.nasm > +; > +; Abstract: > +; > +; Find and call SecStartup > +; > +;------------------------------------------------------------------------------ > + > +SECTION .text > + > +extern ASM_PFX(SecStartup) > +extern ASM_PFX(PlatformInit) > + > +global ASM_PFX(CallPeiCoreEntryPoint) > +ASM_PFX(CallPeiCoreEntryPoint): > + ; > + ; Obtain the hob list pointer > + ; > + mov eax, [esp+4] > + ; > + ; Obtain the stack information > + ; ECX: start of range > + ; EDX: end of range > + ; > + mov ecx, [esp+8] > + mov edx, [esp+0xC] > + > + ; > + ; Platform init > + ; > + pushad > + push edx > + push ecx > + push eax > + call ASM_PFX(PlatformInit) > + pop eax > + pop eax > + pop eax > + popad > + > + ; > + ; Set stack top pointer > + ; > + mov esp, edx > + > + ; > + ; Push the hob list pointer > + ; > + push eax > + > + ; > + ; Save the value > + ; ECX: start of range > + ; EDX: end of range > + ; > + mov ebp, esp > + push ecx > + push edx > + > + ; > + ; Push processor count to stack first, then BIST status (AP then BSP) > + ; > + mov eax, 1 > + cpuid > + shr ebx, 16 > + and ebx, 0xFF > + cmp bl, 1 > + jae PushProcessorCount > + > + ; > + ; Some processors report 0 logical processors. Effectively 0 = 1. > + ; So we fix up the processor count > + ; > + inc ebx > + > +PushProcessorCount: > + push ebx > + > + ; > + ; We need to implement a long-term solution for BIST capture. For now, we > just copy BSP BIST > + ; for all processor threads > + ; > + xor ecx, ecx > + mov cl, bl > +PushBist: > + movd eax, mm0 > + push eax > + loop PushBist > + > + ; Save Time-Stamp Counter > + movd eax, mm5 > + push eax > + > + movd eax, mm6 > + push eax > + > + ; > + ; Pass entry point of the PEI core > + ; > + mov edi, 0xFFFFFFE0 > + push DWORD [edi] > + > + ; > + ; Pass BFV into the PEI Core > + ; > + mov edi, 0xFFFFFFFC > + push DWORD [edi] > + > + ; > + ; Pass stack size into the PEI Core > + ; > + mov ecx, [ebp - 4] > + mov edx, [ebp - 8] > + push ecx ; RamBase > + > + sub edx, ecx > + push edx ; RamSize > + > + ; > + ; Pass Control into the PEI Core > + ; > + call ASM_PFX(SecStartup) > + > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm > new file mode 100644 > index 00000000..c4533da1 > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm > @@ -0,0 +1,361 @@ > +;------------------------------------------------------------------------------ > +; > +; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> > +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; Module Name: > +; > +; SecEntry.nasm > +; > +; Abstract: > +; > +; This is the code that goes from real-mode to protected mode. > +; It consumes the reset vector, calls TempRamInit API from FSP binary. > +; > +;------------------------------------------------------------------------------ > + > +#include "Fsp.h" > + > +SECTION .text > + > +extern ASM_PFX(CallPeiCoreEntryPoint) > +extern ASM_PFX(FsptUpdDataPtr) > +extern ASM_PFX(BoardBeforeTempRamInit) > +; Pcds > +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) > +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress)) > + > +;---------------------------------------------------------------------------- > +; > +; Procedure: _ModuleEntryPoint > +; > +; Input: None > +; > +; Output: None > +; > +; Destroys: Assume all registers > +; > +; Description: > +; > +; Transition to non-paged flat-model protected mode from a > +; hard-coded GDT that provides exactly two descriptors. > +; This is a bare bones transition to protected mode only > +; used for a while in PEI and possibly DXE. > +; > +; After enabling protected mode, a far jump is executed to > +; transfer to PEI using the newly loaded GDT. > +; > +; Return: None > +; > +; MMX Usage: > +; MM0 = BIST State > +; MM5 = Save time-stamp counter value high32bit > +; MM6 = Save time-stamp counter value low32bit. > +; > +;---------------------------------------------------------------------------- > + > +BITS 16 > +align 4 > +global ASM_PFX(_ModuleEntryPoint) > +ASM_PFX(_ModuleEntryPoint): > + fninit ; clear any pending Floating point > exceptions > + ; > + ; Store the BIST value in mm0 > + ; > + movd mm0, eax > + cli > + > + ; > + ; Check INIT# is asserted by port 0xCF9 > + ; > + mov dx, 0CF9h > + in al, dx > + cmp al, 04h > + jnz NotWarmStart > + > + > + ; > + ; @note Issue warm reset, since if CPU only reset is issued not all MSRs > are restored to their defaults > + ; > + mov dx, 0CF9h > + mov al, 06h > + out dx, al > + > +NotWarmStart: > + ; > + ; Save time-stamp counter value > + ; rdtsc load 64bit time-stamp counter to EDX:EAX > + ; > + rdtsc > + movd mm5, edx > + movd mm6, eax > + > + ; > + ; Load the GDT table in GdtDesc > + ; > + mov esi, GdtDesc > + DB 66h > + lgdt [cs:si] > + > + ; > + ; Transition to 16 bit protected mode > + ; > + mov eax, cr0 ; Get control register 0 > + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1) > + mov cr0, eax ; Activate protected mode > + > + mov eax, cr4 ; Get control register 4 > + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT > bit (bit #10) > + mov cr4, eax > + > + ; > + ; Now we're in 16 bit protected mode > + ; Set up the selectors for 32 bit protected mode entry > + ; > + mov ax, SYS_DATA_SEL > + mov ds, ax > + mov es, ax > + mov fs, ax > + mov gs, ax > + mov ss, ax > + > + ; > + ; Transition to Flat 32 bit protected mode > + ; The jump to a far pointer causes the transition to 32 bit mode > + ; > + mov esi, ProtectedModeEntryLinearAddress > + jmp dword far [cs:si] > + > +;---------------------------------------------------------------------------- > +; > +; Procedure: ProtectedModeEntryPoint > +; > +; Input: None > +; > +; Output: None > +; > +; Destroys: Assume all registers > +; > +; Description: > +; > +; This function handles: > +; Call two basic APIs from FSP binary > +; Initializes stack with some early data (BIST, PEI entry, etc) > +; > +; Return: None > +; > +;---------------------------------------------------------------------------- > + > +BITS 32 > +align 4 > +ProtectedModeEntryPoint: > + ; > + ; Early board hooks > + ; > + mov esp, BoardBeforeTempRamInitRet > + jmp ASM_PFX(BoardBeforeTempRamInit) > + > +BoardBeforeTempRamInitRet: > + > + ; Find the fsp info header > + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))] > + > + mov eax, dword [edi + FVH_SIGINATURE_OFFSET] > + cmp eax, FVH_SIGINATURE_VALID_VALUE > + jnz FspHeaderNotFound > + > + xor eax, eax > + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET] > + cmp ax, 0 > + jnz FspFvExtHeaderExist > + > + xor eax, eax > + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header > + add edi, eax > + jmp FspCheckFfsHeader > + > +FspFvExtHeaderExist: > + add edi, eax > + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header > + add edi, eax > + > + ; Round up to 8 byte alignment > + mov eax, edi > + and al, 07h > + jz FspCheckFfsHeader > + > + and edi, 0FFFFFFF8h > + add edi, 08h > + > +FspCheckFfsHeader: > + ; Check the ffs guid > + mov eax, dword [edi] > + cmp eax, FSP_HEADER_GUID_DWORD1 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 4] > + cmp eax, FSP_HEADER_GUID_DWORD2 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 8] > + cmp eax, FSP_HEADER_GUID_DWORD3 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 0Ch] > + cmp eax, FSP_HEADER_GUID_DWORD4 > + jnz FspHeaderNotFound > + > + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header > + > + ; Check the section type as raw section > + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET] > + cmp al, 019h > + jnz FspHeaderNotFound > + > + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header > + jmp FspHeaderFound > + > +FspHeaderNotFound: > + jmp $ > + > +FspHeaderFound: > + ; Get the fsp TempRamInit Api address > + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] > + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] > + > + ; Setup the hardcode stack > + mov esp, TempRamInitStack > + > + ; Call the fsp TempRamInit Api > + jmp eax > + > +TempRamInitDone: > + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for > Microcode Update not found. > + je CallSecFspInit ;If microcode not found, don't hang, but continue. > + > + cmp eax, 0 ;Check if EFI_SUCCESS retuned. > + jnz FspApiFailed > + > + ; ECX: start of range > + ; EDX: end of range > +CallSecFspInit: > + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam > for FSP > + xor eax, eax > + mov esp, edx > + > + ; Align the stack at DWORD > + add esp, 3 > + and esp, 0FFFFFFFCh > + > + push edx > + push ecx > + push eax ; zero - no hob list yet > + call ASM_PFX(CallPeiCoreEntryPoint) > + > +FspApiFailed: > + jmp $ > + > +align 10h > +TempRamInitStack: > + DD TempRamInitDone > + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams > + > +; > +; ROM-based Global-Descriptor Table for the Tiano PEI Phase > +; > +align 16 > +global ASM_PFX(BootGdtTable) > + > +; > +; GDT[0]: 0x00: Null entry, never used. > +; > +NULL_SEL EQU $ - GDT_BASE ; Selector [0] > +GDT_BASE: > +ASM_PFX(BootGdtTable): > + DD 0 > + DD 0 > +; > +; Linear data segment descriptor > +; > +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 092h ; present, ring 0, data, expand-up, > writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > +; > +; Linear code segment descriptor > +; > +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 09Bh ; present, ring 0, data, expand-up, > not-writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > +; > +; System data segment descriptor > +; > +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 093h ; present, ring 0, data, expand-up, > not-writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > + > +; > +; System code segment descriptor > +; > +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 09Ah ; present, ring 0, data, expand-up, > writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > +; > +; Spare segment descriptor > +; > +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0Eh ; Changed from F000 to E000. > + DB 09Bh ; present, ring 0, code, expand-up, > writable > + DB 00h ; byte-granular, 16-bit > + DB 0 > +; > +; Spare segment descriptor > +; > +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30] > + DW 0FFFFh ; limit 0xFFFF > + DW 0 ; base 0 > + DB 0 > + DB 093h ; present, ring 0, data, expand-up, > not-writable > + DB 00h ; byte-granular, 16-bit > + DB 0 > + > +; > +; Spare segment descriptor > +; > +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38] > + DW 0 ; limit 0 > + DW 0 ; base 0 > + DB 0 > + DB 0 ; present, ring 0, data, expand-up, > writable > + DB 0 ; page-granular, 32-bit > + DB 0 > +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes > + > +; > +; GDT Descriptor > +; > +GdtDesc: ; GDT descriptor > + DW GDT_SIZE - 1 ; GDT limit > + DD GDT_BASE ; GDT base address > + > + > +ProtectedModeEntryLinearAddress: > +ProtectedModeEntryLinear: > + DD ProtectedModeEntryPoint ; Offset of our 32 bit code > + DW LINEAR_CODE_SEL > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm > new file mode 100644 > index 00000000..d893b692 > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm > @@ -0,0 +1,72 @@ > +;------------------------------------------------------------------------------ > +; > +; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> > +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; Abstract: > +; > +; Switch the stack from temporary memory to permanent memory. > +; > +;------------------------------------------------------------------------------ > + > + SECTION .text > + > +;------------------------------------------------------------------------------ > +; VOID > +; EFIAPI > +; SecSwitchStack ( > +; UINT32 TemporaryMemoryBase, > +; UINT32 PermanentMemoryBase > +; ); > +;------------------------------------------------------------------------------ > +global ASM_PFX(SecSwitchStack) > +ASM_PFX(SecSwitchStack): > + ; > + ; Save three register: eax, ebx, ecx > + ; > + push eax > + push ebx > + push ecx > + push edx > + > + ; > + ; !!CAUTION!! this function address's is pushed into stack after > + ; migration of whole temporary memory, so need save it to permanent > + ; memory at first! > + ; > + > + mov ebx, [esp + 20] ; Save the first parameter > + mov ecx, [esp + 24] ; Save the second parameter > + > + ; > + ; Save this function's return address into permanent memory at first. > + ; Then, Fixup the esp point to permanent memory > + ; > + mov eax, esp > + sub eax, ebx > + add eax, ecx > + mov edx, dword [esp] ; copy pushed register's value to > permanent memory > + mov dword [eax], edx > + mov edx, dword [esp + 4] > + mov dword [eax + 4], edx > + mov edx, dword [esp + 8] > + mov dword [eax + 8], edx > + mov edx, dword [esp + 12] > + mov dword [eax + 12], edx > + mov edx, dword [esp + 16] ; Update this function's return address > into permanent memory > + mov dword [eax + 16], edx > + mov esp, eax ; From now, esp is pointed to > permanent memory > + > + ; > + ; Fixup the ebp point to permanent memory > + ; > + mov eax, ebp > + sub eax, ebx > + add eax, ecx > + mov ebp, eax ; From now, ebp is pointed to permanent > memory > + > + pop edx > + pop ecx > + pop ebx > + pop eax > + ret > + > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c > new file mode 100644 > index 00000000..f7ec4f9e > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c > @@ -0,0 +1,47 @@ > +/** @file > + Provide platform init function. > + > +Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > + > +#include <PiPei.h> > +#include <Library/DebugLib.h> > +#include <Library/SerialPortLib.h> > +#include <Library/SecBoardInitLib.h> > +#include <Library/TestPointCheckLib.h> > + > +/** > + Platform initialization. > + > + @param[in] FspHobList HobList produced by FSP. > + @param[in] StartOfRange Start of temporary RAM. > + @param[in] EndOfRange End of temporary RAM. > +**/ > +VOID > +EFIAPI > +PlatformInit ( > + IN VOID *FspHobList, > + IN VOID *StartOfRange, > + IN VOID *EndOfRange > + ) > +{ > + // > + // Platform initialization > + // Enable Serial port here > + // > + if (PcdGetBool(PcdSecSerialPortDebugEnable)) { > + SerialPortInitialize (); > + } > + > + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n")); > + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList)); > + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange)); > + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange)); > + > + BoardAfterTempRamInit (); > + > + TestPointTempMemoryFunction (StartOfRange, EndOfRange); > +} > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > new file mode 100644 > index 00000000..71c19d1c > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > @@ -0,0 +1,106 @@ > +## @file > +# Provide FSP wrapper platform sec related function. > +# > +# Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR> > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +################################################################################ > +# > +# Defines Section - statements that will be processed to create a Makefile. > +# > +################################################################################ > +[Defines] > + INF_VERSION = 0x00010005 > + BASE_NAME = SecFspWrapperPlatformSecLib > + FILE_GUID = 5C3B04E1-60BC-4CE7-AD6B-60E395EF0051 > + MODULE_TYPE = SEC > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PlatformSecLib > + > + > +# > +# The following information is for reference only and not required by the > build tools. > +# > +# VALID_ARCHITECTURES = IA32 X64 > +# > + > +################################################################################ > +# > +# Sources Section - list of files that are required for the build to succeed. > +# > +################################################################################ > + > +[Sources] > + FspWrapperPlatformSecLib.c > + SecRamInitData.c > + SecPlatformInformation.c > + SecGetPerformance.c > + SecTempRamDone.c > + PlatformInit.c > + FsptCoreUpd.h > + > +[Sources.IA32] > + Ia32/SecEntry.nasm > + Ia32/PeiCoreEntry.nasm > + Ia32/Stack.nasm > + Ia32/Fsp.h > + > +################################################################################ > +# > +# Package Dependency Section - list of Package files that are required for > +# this module. > +# > +################################################################################ > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + IntelFsp2Pkg/IntelFsp2Pkg.dec > + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + AlderlakeSiliconPkg/SiPkg.dec > + AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec > + AlderlakeOpenBoardPkg/OpenBoardPkg.dec > + > +[LibraryClasses] > + LocalApicLib > + SerialPortLib > + FspWrapperPlatformLib > + FspWrapperApiLib > + SecBoardInitLib > + TestPointCheckLib > + PeiServicesTablePointerLib > + > +[Ppis] > + gEfiSecPlatformInformationPpiGuid ## CONSUMES > + gPeiSecPerformancePpiGuid ## CONSUMES > + gTopOfTemporaryRamPpiGuid ## PRODUCES > + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES > + gFspTempRamExitPpiGuid ## CONSUMES > + gPlatformInitTempRamExitPpiGuid ## CONSUMES > + > +[Pcd] > + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## > CONSUMES > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## > CONSUMES > + > +[FixedPcd] > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## > CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## > CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## > CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartMode ## > CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate ## > CONSUMES > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## > PRODUCES > + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## > CONSUMES > \ No newline at end of file > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c > new file mode 100644 > index 00000000..a59ee9a3 > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c > @@ -0,0 +1,89 @@ > +/** @file > + Sample to provide SecGetPerformance function. > + > +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include <PiPei.h> > + > +#include <Ppi/SecPerformance.h> > +#include <Ppi/TopOfTemporaryRam.h> > + > +#include <Library/BaseMemoryLib.h> > +#include <Library/TimerLib.h> > +#include <Library/DebugLib.h> > + > +/** > + This interface conveys performance information out of the Security (SEC) > phase into PEI. > + > + This service is published by the SEC phase. The SEC phase handoff has an > optional > + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed > from SEC into the > + PEI Foundation. As such, if the platform supports collecting performance > data in SEC, > + this information is encapsulated into the data structure abstracted by > this service. > + This information is collected for the boot-strap processor (BSP) on IA-32. > + > + @param[in] PeiServices The pointer to the PEI Services Table. > + @param[in] This The pointer to this instance of the > PEI_SEC_PERFORMANCE_PPI. > + @param[out] Performance The pointer to performance data collected in SEC > phase. > + > + @retval EFI_SUCCESS The data was successfully returned. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecGetPerformance ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN PEI_SEC_PERFORMANCE_PPI *This, > + OUT FIRMWARE_SEC_PERFORMANCE *Performance > + ) > +{ > + UINT32 Size; > + UINT32 Count; > + UINTN TopOfTemporaryRam; > + UINT64 Ticker; > + VOID *TopOfTemporaryRamPpi; > + EFI_STATUS Status; > + > + DEBUG ((DEBUG_INFO, "SecGetPerformance\n")); > + > + Status = (*PeiServices)->LocatePpi ( > + PeiServices, > + &gTopOfTemporaryRamPpiGuid, > + 0, > + NULL, > + (VOID **) &TopOfTemporaryRamPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + // > + // |--------------| <- TopOfTemporaryRam - BL > + // | List Ptr | > + // |--------------| > + // | BL RAM Start | > + // |--------------| > + // | BL RAM End | > + // |--------------| > + // |Number of BSPs| > + // |--------------| > + // | BIST | > + // |--------------| > + // | .... | > + // |--------------| > + // | TSC[63:32] | > + // |--------------| > + // | TSC[31:00] | > + // |--------------| > + // > + TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); > + TopOfTemporaryRam -= sizeof (UINT32) * 2; > + Count = *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)); > + Size = Count * sizeof (UINT32); > + > + Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof > (UINT32) * 2); > + Performance->ResetEnd = GetTimeInNanoSecond (Ticker); > + > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c > new file mode 100644 > index 00000000..401f84e5 > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c > @@ -0,0 +1,78 @@ > +/** @file > + Provide SecPlatformInformation function. > + > +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include <PiPei.h> > + > +#include <Ppi/SecPlatformInformation.h> > +#include <Ppi/TopOfTemporaryRam.h> > + > +#include <Library/BaseMemoryLib.h> > +#include <Library/DebugLib.h> > + > +/** > + This interface conveys state information out of the Security (SEC) phase > into PEI. > + > + @param[in] PeiServices Pointer to the PEI Services Table. > + @param[in,out] StructureSize Pointer to the variable > describing size of the input buffer. > + @param[out] PlatformInformationRecord Pointer to the > EFI_SEC_PLATFORM_INFORMATION_RECORD. > + > + @retval EFI_SUCCESS The data was successfully returned. > + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecPlatformInformation ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN OUT UINT64 *StructureSize, > + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord > + ) > +{ > + UINT32 *Bist; > + UINT32 Size; > + UINT32 Count; > + UINTN TopOfTemporaryRam; > + VOID *TopOfTemporaryRamPpi; > + EFI_STATUS Status; > + > + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n")); > + > + Status = (*PeiServices)->LocatePpi ( > + PeiServices, > + &gTopOfTemporaryRamPpiGuid, > + 0, > + NULL, > + (VOID **) &TopOfTemporaryRamPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + // > + // The entries of BIST information, together with the number of them, > + // reside in the bottom of stack, left untouched by normal stack operation. > + // This routine copies the BIST information to the buffer pointed by > + // PlatformInformationRecord for output. > + // > + TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); > + TopOfTemporaryRam -= sizeof (UINT32) * 2; > + Count = *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32))); > + Size = Count * sizeof (IA32_HANDOFF_STATUS); > + > + if ((*StructureSize) < (UINT64) Size) { > + *StructureSize = Size; > + return EFI_BUFFER_TOO_SMALL; > + } > + > + *StructureSize = Size; > + Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size); > + > + CopyMem (PlatformInformationRecord, Bist, Size); > + > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c > new file mode 100644 > index 00000000..a3cc8741 > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c > @@ -0,0 +1,57 @@ > +/** @file > + Provide TempRamInitParams data. > + > +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include <Library/PcdLib.h> > +#include <FspEas.h> > +#include "FsptCoreUpd.h" > + > +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr = { > + { > + FSPT_UPD_SIGNATURE, > + 0x02, > + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00 > + } > + }, > + { > + 0x01, > + { > + 0x00, 0x00, 0x00 > + }, > + 0x00000020, > + 0x00000000, > + { > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + } > + }, > + { > + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 > (PcdMicrocodeOffsetInFv), > + FixedPcdGet64 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 > (PcdMicrocodeOffsetInFv), > + 0, // Set CodeRegionBase as 0, so that caching will be > 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. > + FixedPcdGet32 (PcdFlashCodeCacheSize), > + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + } > + }, > + { > + FixedPcdGet8 (PcdSerialIoUartDebugEnable), > + FixedPcdGet8 (PcdSerialIoUartNumber), > + FixedPcdGet8 (PcdSerialIoUartMode), > + 0, > + FixedPcdGet32 (PcdSerialIoUartBaudRate), > + FixedPcdGet64 (PcdPciExpressBaseAddress), > + { > + 0x00 > + } > + }, > + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + }, > + 0x55AA > +}; > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c > new file mode 100644 > index 00000000..d28e9b7c > --- /dev/null > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c > @@ -0,0 +1,93 @@ > +/** @file > + Provide SecTemporaryRamDone function. > + > +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR> > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include <PiPei.h> > + > +#include <Ppi/TemporaryRamDone.h> > +#include <Ppi/TempRamExitPpi.h> > +#include <Ppi/PlatformInitTempRamExitPpi.h> > + > +#include <Library/BaseMemoryLib.h> > +#include <Library/DebugLib.h> > +#include <Library/PcdLib.h> > +#include <Library/DebugAgentLib.h> > +#include <Library/FspWrapperPlatformLib.h> > +#include <Library/FspWrapperApiLib.h> > +#include <Library/PeiServicesTablePointerLib.h> > + > +/** > +This interface disables temporary memory in SEC Phase. > +**/ > +VOID > +EFIAPI > +SecPlatformDisableTemporaryMemory ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + VOID *TempRamExitParam; > + CONST EFI_PEI_SERVICES **PeiServices; > + FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi; > + PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi; > + > + DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); > + PeiServices = GetPeiServicesTablePointer (); > + ASSERT (PeiServices != NULL); > + if (PeiServices == NULL) { > + return; > + } > + ASSERT ((*PeiServices) != NULL); > + if ((*PeiServices) == NULL) { > + return; > + } > + Status = (*PeiServices)->LocatePpi ( > + PeiServices, > + &gPlatformInitTempRamExitPpiGuid, > + 0, > + NULL, > + (VOID **) &PlatformInitTempRamExitPpi > + ); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return; > + } > + > + Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit (); > + ASSERT_EFI_ERROR (Status); > + > + if (PcdGet8 (PcdFspModeSelection) == 1) { > + // > + // FSP API mode > + // > + TempRamExitParam = UpdateTempRamExitParam (); > + Status = CallTempRamExit (TempRamExitParam); > + DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status)); > + ASSERT_EFI_ERROR (Status); > + } else { > + // > + // FSP Dispatch mode > + // > + Status = (*PeiServices)->LocatePpi ( > + PeiServices, > + &gFspTempRamExitPpiGuid, > + 0, > + NULL, > + (VOID **) &TempRamExitPpi > + ); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return; > + } > + TempRamExitPpi->TempRamExit (NULL); > + } > + > + Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit (); > + ASSERT_EFI_ERROR (Status); > + > + return ; > +} > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h > b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h > deleted file mode 100644 > index 76ba3a80..00000000 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h > +++ /dev/null > @@ -1,99 +0,0 @@ > -/** @file > - The header file includes the common header files, defines > - internal structure and functions used by SpiFlashCommonLib. > - > - Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > -**/ > - > -#ifndef __SPI_FLASH_COMMON_H__ > -#define __SPI_FLASH_COMMON_H__ > - > -#include <Uefi.h> > -#include <Library/BaseLib.h> > -#include <Library/PcdLib.h> > -#include <Library/DebugLib.h> > -#include <Library/BaseMemoryLib.h> > -#include <Library/MemoryAllocationLib.h> > -#include <Library/UefiDriverEntryPoint.h> > -#include <Library/UefiBootServicesTableLib.h> > -#include <Protocol/Spi.h> > - > -#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size > -/** > - Enable block protection on the Serial Flash device. > - > - @retval EFI_SUCCESS Opertion is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashLock ( > - VOID > - ); > - > -/** > - Read NumBytes bytes of data from the address specified by > - PAddress into Buffer. > - > - @param[in] Address The starting physical address of the read. > - @param[in,out] NumBytes On input, the number of bytes to read. On > output, the number > - of bytes actually read. > - @param[out] Buffer The destination data buffer for the read. > - > - @retval EFI_SUCCESS Opertion is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashRead ( > - IN UINTN Address, > - IN OUT UINT32 *NumBytes, > - OUT UINT8 *Buffer > - ); > - > -/** > - Write NumBytes bytes of data from Buffer to the address specified by > - PAddresss. > - > - @param[in] Address The starting physical address of the write. > - @param[in,out] NumBytes On input, the number of bytes to write. On > output, > - the actual number of bytes written. > - @param[in] Buffer The source data buffer for the write. > - > - @retval EFI_SUCCESS Opertion is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashWrite ( > - IN UINTN Address, > - IN OUT UINT32 *NumBytes, > - IN UINT8 *Buffer > - ); > - > -/** > - Erase the block starting at Address. > - > - @param[in] Address The starting physical address of the block to > be erased. > - This library assume that caller garantee that > the PAddress > - is at the starting address of this block. > - @param[in] NumBytes On input, the number of bytes of the logical > block to be erased. > - On output, the actual number of bytes erased. > - > - @retval EFI_SUCCESS. Opertion is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashBlockErase ( > - IN UINTN Address, > - IN UINTN *NumBytes > - ); > - > -#endif > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf > > b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf > deleted file mode 100644 > index cf6ca0d0..00000000 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf > +++ /dev/null > @@ -1,49 +0,0 @@ > -### @file > -# SMM Library instance of Spi Flash Common Library Class > -# > -# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > -# SPDX-License-Identifier: BSD-2-Clause-Patent > -# > -### > - > -[Defines] > - INF_VERSION = 0x00010017 > - BASE_NAME = SmmSpiFlashCommonLib > - FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47 > - VERSION_STRING = 1.0 > - MODULE_TYPE = DXE_SMM_DRIVER > - LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER > - CONSTRUCTOR = SmmSpiFlashCommonLibConstructor > -# > -# The following information is for reference only and not required by the > build tools. > -# > -# VALID_ARCHITECTURES = IA32 X64 > -# > - > -[LibraryClasses] > - IoLib > - MemoryAllocationLib > - BaseLib > - UefiLib > - SmmServicesTableLib > - BaseMemoryLib > - DebugLib > - > -[Packages] > - MdePkg/MdePkg.dec > - AlderlakeSiliconPkg/SiPkg.dec > - AlderlakeOpenBoardPkg/OpenBoardPkg.dec > - > -[Pcd] > - gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES > - gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES > - > -[Sources] > - SpiFlashCommonSmmLib.c > - SpiFlashCommon.c > - > -[Protocols] > - gPchSmmSpiProtocolGuid ## CONSUMES > - > -[Depex.X64.DXE_SMM_DRIVER] > - gPchSmmSpiProtocolGuid > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c > deleted file mode 100644 > index 3f7c52ac..00000000 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c > +++ /dev/null > @@ -1,215 +0,0 @@ > -/** @file > - Wrap EFI_SPI_PROTOCOL to provide some library level interfaces > - for module use. > - > - Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > - > -**/ > - > -#include <Library/SpiFlashCommon.h> > -#include <Library/IoLib.h> > - > -PCH_SPI_PROTOCOL *mSpiProtocol; > - > -// > -// Variables for boottime and runtime usage. > -// > -UINTN mBiosAreaBaseAddress = 0; > -UINTN mBiosSize = 0; > -UINTN mBiosOffset = 0; > - > -/** > - Enable block protection on the Serial Flash device. > - > - @retval EFI_SUCCESS Operation is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashLock ( > - VOID > - ) > -{ > - EFI_STATUS Status; > - > - Status = EFI_SUCCESS; > - > - return Status; > -} > - > -/** > - Read NumBytes bytes of data from the address specified by > - PAddress into Buffer. > - > - @param[in] Address The starting physical address of the read. > - @param[in,out] NumBytes On input, the number of bytes to read. On > output, the number > - of bytes actually read. > - @param[out] Buffer The destination data buffer for the read. > - > - @retval EFI_SUCCESS Operation is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashRead ( > - IN UINTN Address, > - IN OUT UINT32 *NumBytes, > - OUT UINT8 *Buffer > - ) > -{ > - ASSERT ((NumBytes != NULL) && (Buffer != NULL)); > - if ((NumBytes == NULL) || (Buffer == NULL)) { > - return EFI_INVALID_PARAMETER; > - } > - > - // > - // This function is implemented specifically for those platforms > - // at which the SPI device is memory mapped for read. So this > - // function just do a memory copy for Spi Flash Read. > - // > - CopyMem (Buffer, (VOID *) Address, *NumBytes); > - > - return EFI_SUCCESS; > -} > - > -/** > - Write NumBytes bytes of data from Buffer to the address specified by > - PAddresss. > - > - @param[in] Address The starting physical address of the write. > - @param[in,out] NumBytes On input, the number of bytes to write. On > output, > - the actual number of bytes written. > - @param[in] Buffer The source data buffer for the write. > - > - @retval EFI_SUCCESS Operation is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - @retval EFI_INVALID_PARAMETER Invalid parameter. > - @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header > exceeds the > - size ofBIOS Guard script buffer > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashWrite ( > - IN UINTN Address, > - IN OUT UINT32 *NumBytes, > - IN UINT8 *Buffer > - ) > -{ > - EFI_STATUS Status; > - UINTN Offset; > - UINT32 Length; > - UINT32 RemainingBytes; > - > - ASSERT ((NumBytes != NULL) && (Buffer != NULL)); > - if ((NumBytes == NULL) || (Buffer == NULL)) { > - return EFI_INVALID_PARAMETER; > - } > - > - ASSERT (Address >= mBiosAreaBaseAddress); > - if (Address < mBiosAreaBaseAddress) { > - return EFI_INVALID_PARAMETER; > - } > - > - Offset = Address - mBiosAreaBaseAddress; > - > - ASSERT ((*NumBytes + Offset) <= mBiosSize); > - if ((*NumBytes + Offset) > mBiosSize) { > - return EFI_INVALID_PARAMETER; > - } > - > - Status = EFI_SUCCESS; > - RemainingBytes = *NumBytes; > - > - while (RemainingBytes > 0) { > - if (RemainingBytes > SECTOR_SIZE_4KB) { > - Length = SECTOR_SIZE_4KB; > - } else { > - Length = RemainingBytes; > - } > - Status = mSpiProtocol->FlashWrite ( > - mSpiProtocol, > - FlashRegionBios, > - (UINT32) Offset, > - Length, > - Buffer > - ); > - if (EFI_ERROR (Status)) { > - break; > - } > - RemainingBytes -= Length; > - Offset += Length; > - Buffer += Length; > - } > - > - // > - // Actual number of bytes written > - // > - *NumBytes -= RemainingBytes; > - > - return Status; > -} > - > -/** > - Erase the block starting at Address. > - > - @param[in] Address The starting physical address of the block to > be erased. > - This library assume that caller garantee that > the PAddress > - is at the starting address of this block. > - @param[in] NumBytes On input, the number of bytes of the logical > block to be erased. > - On output, the actual number of bytes erased. > - > - @retval EFI_SUCCESS. Operation is successful. > - @retval EFI_DEVICE_ERROR If there is any device errors. > - @retval EFI_INVALID_PARAMETER Invalid parameter. > - > -**/ > -EFI_STATUS > -EFIAPI > -SpiFlashBlockErase ( > - IN UINTN Address, > - IN UINTN *NumBytes > - ) > -{ > - EFI_STATUS Status; > - UINTN Offset; > - UINTN RemainingBytes; > - > - ASSERT (NumBytes != NULL); > - if (NumBytes == NULL) { > - return EFI_INVALID_PARAMETER; > - } > - > - ASSERT (Address >= mBiosAreaBaseAddress); > - if (Address < mBiosAreaBaseAddress) { > - return EFI_INVALID_PARAMETER; > - } > - > - Offset = Address - mBiosAreaBaseAddress; > - > - ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0); > - if ((*NumBytes % SECTOR_SIZE_4KB) != 0) { > - return EFI_INVALID_PARAMETER; > - } > - > - ASSERT ((*NumBytes + Offset) <= mBiosSize); > - if ((*NumBytes + Offset) > mBiosSize) { > - return EFI_INVALID_PARAMETER; > - } > - > - Status = EFI_SUCCESS; > - RemainingBytes = *NumBytes; > - > - Status = mSpiProtocol->FlashErase ( > - mSpiProtocol, > - FlashRegionBios, > - (UINT32) Offset, > - (UINT32) RemainingBytes > - ); > - return Status; > -} > - > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c > deleted file mode 100644 > index 897d8574..00000000 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c > +++ /dev/null > @@ -1,60 +0,0 @@ > -/** @file > - SMM Library instance of SPI Flash Common Library Class > - > - Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > - > -**/ > - > -#include <Library/SpiFlashCommon.h> > -#include <Library/SmmServicesTableLib.h> > - > -extern PCH_SPI_PROTOCOL *mSpiProtocol; > - > -extern UINTN mBiosAreaBaseAddress; > -extern UINTN mBiosSize; > -extern UINTN mBiosOffset; > - > -/** > - The library constructuor. > - > - The function does the necessary initialization work for this library > - instance. > - > - @param[in] ImageHandle The firmware allocated handle for the UEFI > image. > - @param[in] SystemTable A pointer to the EFI system table. > - > - @retval EFI_SUCCESS The function always return EFI_SUCCESS for > now. > - It will ASSERT on error for debug version. > - @retval EFI_ERROR Please reference LocateProtocol for error > code details. > -**/ > -EFI_STATUS > -EFIAPI > -SmmSpiFlashCommonLibConstructor ( > - IN EFI_HANDLE ImageHandle, > - IN EFI_SYSTEM_TABLE *SystemTable > - ) > -{ > - EFI_STATUS Status; > - UINT32 BaseAddr; > - UINT32 RegionSize; > - > - mBiosAreaBaseAddress = (UINTN) PcdGet32 (PcdBiosAreaBaseAddress); > - mBiosSize = (UINTN) PcdGet32 (PcdBiosSize); > - > - // > - // Locate the SMM SPI protocol. > - // > - Status = gSmst->SmmLocateProtocol ( > - &gPchSmmSpiProtocolGuid, > - NULL, > - (VOID **) &mSpiProtocol > - ); > - ASSERT_EFI_ERROR (Status); > - > - mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr, > &RegionSize); > - mBiosOffset = BaseAddr; > - > - return Status; > -} > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c > index 4fab4ad8..fab53ed8 100644 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c > @@ -5,52 +5,14 @@ > SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > - > -#include <Register/Msr.h> > -#include <CpuRegs.h> > -#include <Library/IoLib.h> > #include <Library/HobLib.h> > #include <Library/DebugLib.h> > -#include <Library/PchInfoLib.h> > #include <Library/BaseMemoryLib.h> > #include <Library/PeiServicesLib.h> > -#include <Ppi/EndOfPeiPhase.h> > -#include <Library/MtrrLib.h> > -#include <Ppi/ReadOnlyVariable2.h> > -#include <Guid/SmramMemoryReserve.h> > -#include <Library/ConfigBlockLib.h> > -#include <Ppi/SiPolicy.h> > -#include <PchPolicyCommon.h> > -#include <Library/SiPolicyLib.h> > -#include <Guid/FirmwareFileSystem2.h> > -#include <Protocol/FirmwareVolumeBlock.h> > -#include <Library/PostCodeLib.h> > -#include <PlatformPostCode.h> > -#include <Ppi/Spi.h> > -#include <Library/MtrrLib.h> > -#include <Library/PciSegmentLib.h> > -#include <Register/PchRegs.h> > -#include <PlatformBoardId.h> > #include <Core/Pei/PeiMain.h> > -#include <Library/PchPciBdfLib.h> > #include <Ppi/GraphicsPlatformPolicyPpi.h> > #include <Library/PeiGetFvInfoLib.h> > > - > -EFI_STATUS > -EFIAPI > -OpenBoardPlatformInitEndOfPei ( > - IN CONST EFI_PEI_SERVICES **PeiServices, > - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, > - IN VOID *Ppi > - ); > - > -static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = { > - (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), > - &gEfiEndOfPeiSignalPpiGuid, > - (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei > -}; > - > EFI_STATUS > EFIAPI > GetPeiPlatformLidStatus ( > @@ -127,58 +89,10 @@ GetPeiPlatformLidStatus ( > OUT LID_STATUS *CurrentLidStatus > ) > { > - DEBUG ((DEBUG_INFO, "LidStatus Unsupported\n")); > - return EFI_UNSUPPORTED; > -} > - > -/** > - Configure PciHostBridge related PCDs > -**/ > -VOID > -ConfigurePciHostBridgePcds ( > - VOID > - ) > -{ > - // > - // Provide 256GB available above 4GB MMIO resource > - // limited to use single variable MTRR to cover this above 4GB MMIO region. > - // > - PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB); > - PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB - 1); > - if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 > (PcdPciReservedMemAbove4GBLimit)) { > - DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", > PcdGet64 (PcdPciReservedMemAbove4GBBase))); > - DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64 > (PcdPciReservedMemAbove4GBLimit))); > - } > -} > - > -/** > - This function handles PlatformInit task at the end of PEI > - > - @param[in] PeiServices Pointer to PEI Services Table. > - @param[in] NotifyDesc Pointer to the descriptor for the Notification > event that > - caused this function to execute. > - @param[in] Ppi Pointer to the PPI data associated with this > function. > - > - @retval EFI_SUCCESS The function completes successfully > - @retval others > -**/ > -EFI_STATUS > -EFIAPI > -OpenBoardPlatformInitEndOfPei ( > - IN CONST EFI_PEI_SERVICES **PeiServices, > - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, > - IN VOID *Ppi > - ) > -{ > - // > - // Configure PciHostBridge related PCDs before DXE phase > - // > - ConfigurePciHostBridgePcds (); > - > + *CurrentLidStatus = LidOpen; > return EFI_SUCCESS; > } > > - > /** > Platform Init PEI module entry point > > @@ -201,8 +115,6 @@ OpenBoardPlatformInitPostMemEntryPoint ( > PEI_CORE_FV_HANDLE *CoreFvHandle; > VOID *HobData; > > - PostCode (PLATFORM_INIT_POSTMEM_ENTRY); > - > // > // Build a HOB to show current FV location for SA policy update code to > consume. > // > @@ -223,11 +135,5 @@ OpenBoardPlatformInitPostMemEntryPoint ( > DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n")); > Status = PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi); > > - // > - // Performing PlatformInitEndOfPei after EndOfPei PPI produced > - // > - Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList); > - PostCode (PLATFORM_INIT_POSTMEM_EXIT); > - > return Status; > } > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf > > b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf > index b2bfd97f..31c01919 100644 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf > @@ -17,20 +17,11 @@ > [LibraryClasses] > PeimEntryPoint > DebugLib > - IoLib > MemoryAllocationLib > BaseMemoryLib > HobLib > PeiServicesLib > - PciSegmentLib > - MtrrLib > - PchInfoLib > - PostCodeLib > - SiPolicyLib > - FspCommonLib > PcdLib > - PchPciBdfLib > - GpioLib > PeiGetFvInfoLib > > [Packages] > @@ -49,27 +40,16 @@ > OpenBoardPlatformInitPostMem.c > > [Ppis] > - gEfiEndOfPeiSignalPpiGuid ## CONSUMES > - gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES > gPeiGraphicsPlatformPpiGuid ## PRODUCES > - gFspSiliconInitDonePpiGuid ## CONSUMES > > [Protocols] > > [Guids] > - gEfiSmmSmramMemoryGuid ## CONSUMES > gPlatformInitFvLocationGuid ## PRODUCES > > [Depex] > gEfiPeiMemoryDiscoveredPpiGuid > > [Pcd] > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES > - gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES > - > gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES > > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c > index da2f568e..fac1fb7a 100644 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c > @@ -10,7 +10,32 @@ > #include <Library/DebugLib.h> > #include <Library/UefiBootServicesTableLib.h> > #include <Library/GraphicsInfoLib.h> > +#include <Library/UefiLib.h> > + > #include <Protocol/SaPolicy.h> > +#include <Protocol/PciEnumerationComplete.h> > + > +// > +// The boot script private data. > +// > +typedef struct { > + UINT8 *TableBase; > + UINT32 TableLength; // Record the actual memory length > + UINT16 TableMemoryPageNumber; // Record the page number Allocated for > the table > + BOOLEAN InSmm; // Record if this library is in SMM. > + BOOLEAN AtRuntime; // Record if current state is after > SmmExitBootServices or SmmLegacyBoot. > + UINT32 BootTimeScriptLength; // Maintain boot time script length in > LockBox after SmmReadyToLock in SMM. > + BOOLEAN SmmLocked; // Record if current state is after > SmmReadyToLock > + BOOLEAN BackFromS3; // Indicate that the system is back from > S3. > +} SCRIPT_TABLE_PRIVATE_DATA; > + > +SCRIPT_TABLE_PRIVATE_DATA *mS3BootScriptTablePtr; > +VOID > +EFIAPI > +S3SmmLockedCallback ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ); > > EFI_STATUS > EFIAPI > @@ -43,6 +68,7 @@ SaPolicyInitDxe ( > { > EFI_STATUS Status; > SA_POLICY_PROTOCOL *SaPolicy; > + VOID *Registration; > > // > // Call CreateSaDxeConfigBlocks to create & initialize platform policy > structure > @@ -52,6 +78,17 @@ SaPolicyInitDxe ( > DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", > SaPolicy->TableHeader.NumberOfBlocks)); > ASSERT_EFI_ERROR (Status); > > + /// > + /// Create S3 SmmLocked callback to fix assert > + /// > + EfiCreateProtocolNotifyEvent ( > + &gEfiPciEnumerationCompleteProtocolGuid, > + TPL_CALLBACK, > + S3SmmLockedCallback, > + NULL, > + &Registration > + ); > + > // > // Install SaInstallPolicyProtocol. > // While installed, RC assumes the Policy is ready and finalized. So please > @@ -62,3 +99,37 @@ SaPolicyInitDxe ( > > return EFI_SUCCESS; > } > + > +/** > + This function gets registered as a callback to Enable S3 SmmLocked before > EndOfDxe > + > + @param[in] Event - A pointer to the Event that triggered the callback. > + @param[in] Context - A pointer to private data registered with the > callback function. > +**/ > +VOID > +EFIAPI > +S3SmmLockedCallback ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ) > +{ > + EFI_STATUS Status; > + VOID *ProtocolPointer; > + SCRIPT_TABLE_PRIVATE_DATA *S3TablePtr; > + > + DEBUG ((DEBUG_INFO, "S3SmmLockedCallback Start\n")); > + > + Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, > NULL, (VOID **) &ProtocolPointer); > + if (EFI_SUCCESS != Status) { > + return; > + } > + > + gBS->CloseEvent (Event); > + > + S3TablePtr = (SCRIPT_TABLE_PRIVATE_DATA *)(UINTN)PcdGet64 > (PcdS3BootScriptTablePrivateDataPtr); > + mS3BootScriptTablePtr = S3TablePtr; > + mS3BootScriptTablePtr->SmmLocked = TRUE; > + > + DEBUG ((DEBUG_INFO, "S3SmmLockedCallback End\n")); > + return; > +} > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf > > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf > index 54b4d7b1..25fc411b 100644 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf > @@ -42,12 +42,14 @@ > gBoardModuleTokenSpaceGuid.PcdIntelGopEnable > gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid > gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo ## > CONSUMES > + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr > > [Protocols] > gEfiFirmwareVolume2ProtocolGuid ## CONSUMES > gSaPolicyProtocolGuid ## CONSUMES > gDxeSiPolicyProtocolGuid ## PRODUCES > gGopPolicyProtocolGuid ## PRODUCES > + gEfiPciEnumerationCompleteProtocolGuid ## PRODUCES > > [Depex] > gEfiVariableArchProtocolGuid > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c > > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c > index b23e2cec..1139277f 100644 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c > @@ -15,8 +15,6 @@ > #include <Library/PeiSiPolicyUpdateLib.h> > #include <Library/PmcLib.h> > #include <Library/SiPolicyLib.h> > -#include <Library/SpiLib.h> > -#include <Ppi/Spi.h> > #include <Register/CommonMsr.h> > #include <Register/PchRegs.h> > #include <PlatformBoardConfig.h> > @@ -73,7 +71,6 @@ UpdatePeiCpuPolicyPreMem ( > > UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, > CpuSecurityPreMemConfig->SkipStopPbet, FALSE); > > - SpiServiceInit (); > DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n")); > UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, > CpuSecurityPreMemConfig->BiosGuard, CPU_FEATURE_DISABLE); > > diff --git > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf > > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf > index 844e4c99..d6bb07fa 100644 > --- > a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf > +++ > b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf > @@ -32,7 +32,6 @@ > SiPolicyLib > PeiServicesLib > FirmwareBootMediaLib > - SpiLib > BmpSupportLib > PeiGetFvInfoLib > TimerLib > @@ -205,4 +204,4 @@ > gPchPcieConfigGuid ## CONSUMES > gSerialIoConfigGuid ## CONSUMES > gPcieRpPreMemConfigGuid ## CONSUMES > - gSaMiscPeiPreMemConfigGuid ## CONSUMES > + gSaMiscPeiPreMemConfigGuid ## CONSUMES > \ No newline at end of file > -- > 2.26.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117510): https://edk2.groups.io/g/devel/message/117510 Mute This Topic: https://groups.io/mt/105153727/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
