On Mon, Apr 15, 2024 at 01:04:58PM +0000, Wu, Jiaxin wrote:
> Hi Gred,
>
> Because:
> 1) The mode of the CPU check is different between the AMD & OVMF.
> OVMF:
> CpuSaveState->x86.SMMRevId & 0Xffff
>
> AMD:
> LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA
>
> 2) Existing SmBase configuration is different between the AMD & OVMF.
> OVMF:
> AmdCpuState->x64.SMBASE = (UINT32)mSmBaseForAllCpus[CpuIndex];
>
> AMD:
> if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
> CpuSaveState->x86.SMBASE = (UINT32)mSmBaseForAllCpus[CpuIndex];
> } else {
> CpuSaveState->x64.SMBASE = (UINT32)mSmBaseForAllCpus[CpuIndex];
> }
>
> This series patch won't change the existing implementation code logic, so, we
> need override one version for OVMF.
The real question is why do these differences exist and are they
actually needed.
I'd expect the CPU mode check return identical results.
The SmBase configuration for OVMF looks suspicious to me. I'm wondering
whenever the OVMF code actually works in Ia32 builds ...
take care,
Gerd
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