MemoryFence: I know basically the comments and the code.
The comments say that loads/stores *before* it, are completed *before* it. It says nothing about loads/stores *after* it. Is the exact intent, therefore, that loads/stores after it, can complete before it? See, I have some code, with a similar name and meaning: MemoryBarrier(). It starts out like MemoryFence: all loads and stores before it, complete before it. But more so, all loads and stores after it, complete after it. The x86/amd64 implementation of MemoryBarrier with Visual C++ __faststorefence, which is lock or [rsp], 0 on AMD64. Should x86/amd64 MemoryFence do that, or it is meant exactly as commented? Furthermore, the existing EDK2 x86/amd64 MemoryFence for Visual C++ is an empty function. Was the thinking there, that call stores the return address, ret reads it, these being memory operations, force ordering before/after them? But isn’t LTO/LTCG supposed to work? If so, this is entirely unconvincing. It will be optimized to nothing, including no scheduling inhibitions to compiler or processor. It should, probably, at least _ReadWriteBarrier. Which is stronger than intended, but still incredibly weak. It could even then be extern __forceinline, if that helps. EDK2 ARM/ARM64 MemoryFence use dmb so are full barriers already. Should/can ARM/ARM64 be weakened, in fact? Is there a way? With LSE? Really my question is the opposite though. There are many options. Maybe add a new function with the stronger guarantee. Thank you, Jay -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#121829): https://edk2.groups.io/g/devel/message/121829 Mute This Topic: https://groups.io/mt/118201494/21656 Group Owner: [email protected] Unsubscribe: https://edk2.groups.io/g/devel/unsub [[email protected]] -=-=-=-=-=-=-=-=-=-=-=-
