Quanta engineers walked me through the reset and write protect logic and
convinced me that it works correctly.
EC command 0x05 (sent via the port 68/6c pair) will cause the EC to
reset itself and the rest of the system, in the process releasing the
write protect latch.
A note about reading the Quanta schematics: They use "*" instead of e.g.
"NOPOP" for components that are not normally loaded . One such
component had me mightily confused about how the write protect latch
works, until their notation was pointed out to me.
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