Geode 4M paging support is fully compatible with x86 architecture 4M
caching. It is advertised properly in CPUID. It *should* be enabled
and in use in the OLPC builds automatically. (someone with an olpc
handy could dump the tables and check easily)
The bit pointed out in "Data Memory Configuration Register" (address
1800) is for disabling the PTE cache for debug. The 4M PTE cache is
enabled since the bit is clear:
http://dev.laptop.org/attachment/ticket/109/OLPC.prs
The "L2 TLB/DTE Index Register" you pointed out is also for debug, it
is a way to dump out the various paging caches. The bits set in that
register don't affect operation.
So I guess the summation is that no "special" support is required, the
registers should be set properly, and all that is needed to verify is
that the kernel doesn't do something silly and not use them.
On 1/26/07, Zarro Boogs per Child <[EMAIL PROTECTED]> wrote:
#835: Investigate 4M PTE/TLB caching on the Geode
---------------------+------------------------------------------------------
Reporter: marcelo | Owner: marcelo
Type: defect | Status: new
Priority: normal | Milestone: BTest-3
Component: kernel | Keywords:
---------------------+------------------------------------------------------
{{{
> On Wed, Jan 24, 2007 at 04:29:32PM -0500, Andres Salomon wrote:
> > Hi,
> >
> > The olpc-2.6 config that was inherited from Fedora has
> > CONFIG_PHYSICAL_START=0x400000. We're not using kdump, and the geode
> > can't handle big PTEs; any reason why we shouldn't change this back
to
> > the default 0x100000?
>
> Aligning on a 4MB boundary instead of 1MB has theoretical performance
wins.
> (The geode does have large pages right? And largepage TLBs ?)
It does support 4M PTE's, we need to confirm that its functioning
properly though.
It might be incompatible with Intel's implementation and require special
support:
5.5.2.56 Data Memory Configuration Register
Bit Name
11 P4MDIS
Disable 4M PTE Cache.
0: Enable 4M PTEs to be cached. Normal operation.
1: Prevent 4M PTEs from being cached and flush any existing entries.
As for 4M TLB caching:
5.5.2.75 L2 TLB/DTE Index Register
Bit Name
17:16 L2TLB_SEL
0x: Select L2 TLB.
10: Select DTE cache.
11: Select 4M PTE cache.
However I'm not sure that means it supports caching 4M pages in the TLB.
--
Ticket URL: <http://dev.laptop.org/ticket/835>
One Laptop Per Child <http://laptop.org/>
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