After a week of fits and starts, I got suspend-to-RAM and subsequent
wakeup working reliably on B2 XOs. Atest and B1 systems don't work (the
wiring for the wakeup signals on Atest is screwy; B1 wakes up sometimes
but is generally unreliable, perhaps due to the power-on holdoff
required by the FPGA that simulates CaFe).
From the time that power is restored to the CPU, it takes about 25 mS
to wake up.
So far my tests have all been done from Open Firmware. The OFW command
interpreter calls a self-contained save/sleep/restore subroutine. The
same subroutine will be called from the OS in due time. That routine
saves core registers then puts the CPU chipset to sleep. RAM remains
powered in self-refresh mode, but the main power to the CPU chipset is
removed. Upon receipt of a wakeup event, firmware code restores the
core system state and returns from the subroutine.
The main body of the suspend/resume subroutine lives in RAM (for speed)
at the address 0xf0000, an address range that is traditionally (i.e. on
DOS/Windows PCs) used for accessing the BIOS ROM in 16-bit mode. The
size of the routine is about 1K. It is written in assembly language,
and does not depend on any of the Open Firmware Forth infrastructure at
runtime (Open Firmware loads the subroutine into RAM on initial
power-up, but the routine is otherwise self-contained).
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