RISC-V CPUs may provide a scalable vector extension. The length of the
vector registers is implementation specific. QEMU allows to set the vector
length as a CPU property, e.g. '-cpu rva23s64,vlen=256'.
To describe this feature a new CPU tag is introduced:
<vlen value='N'>
According to the RISC-V ISA specification vlen must be a power of 2
in the range 8 to 65536.
A configuration test is provided.
Heinrich Schuchardt (6):
conf: add vlen tag for RISC-V CPUs
schemas: add cpuVlen definition for RISC-V vector length
qemu: validate that CPU vlen is only used with RISC-V
qemu: emit vlen= CPU property on the command line
tests: provide vlen configuration test
docs: add vlen to formatdomain documentation
docs/formatdomain.rst | 13 ++++++++
src/conf/cpu_conf.c | 25 +++++++++++++++
src/conf/cpu_conf.h | 1 +
src/conf/schemas/cputypes.rng | 11 +++++++
src/qemu/qemu_command.c | 3 ++
src/qemu/qemu_validate.c | 9 ++++++
.../riscv64-virt-vlen.riscv64-latest.args | 31 +++++++++++++++++++
.../riscv64-virt-vlen.riscv64-latest.xml | 26 ++++++++++++++++
tests/qemuxmlconfdata/riscv64-virt-vlen.xml | 26 ++++++++++++++++
tests/qemuxmlconftest.c | 2 ++
10 files changed, 147 insertions(+)
create mode 100644 tests/qemuxmlconfdata/riscv64-virt-vlen.riscv64-latest.args
create mode 100644 tests/qemuxmlconfdata/riscv64-virt-vlen.riscv64-latest.xml
create mode 100644 tests/qemuxmlconfdata/riscv64-virt-vlen.xml
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2.53.0
