On Mon, 2026-10-19 at 01:07 +0200, Philippe Mathieu-Daudé wrote:
> RISC-V 'Z' CPU properties were removed in commit 455c0fa9eef,
> for the release v10.1.0. Remove the stale comment.
>
> Fixes: 455c0fa9eef ("target/riscv: remove capital 'Z' CPU
> properties")
> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> docs/about/deprecated.rst | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> index ccbc4219497..368fa1b4ed3 100644
> --- a/docs/about/deprecated.rst
> +++ b/docs/about/deprecated.rst
> @@ -349,30 +349,6 @@ the addition of volatile memory support, it is
> now necessary to distinguish
> between persistent and volatile memory backends. As such, memdev is
> deprecated
> in favor of persistent-memdev.
>
> -
> -RISC-V CPU properties which start with capital 'Z' (since 8.2)
> -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> -
> -All RISC-V CPU properties which start with capital 'Z' are being
> deprecated
> -starting in 8.2. The reason is that they were wrongly added with
> capital 'Z'
> -in the past. CPU properties were later added with lower-case names,
> which
> -is the format we want to use from now on.
> -
> -Users which try to use these deprecated properties will receive a
> warning
> -recommending to switch to their stable counterparts:
> -
> -- "Zifencei" should be replaced with "zifencei"
> -- "Zicsr" should be replaced with "zicsr"
> -- "Zihintntl" should be replaced with "zihintntl"
> -- "Zihintpause" should be replaced with "zihintpause"
> -- "Zawrs" should be replaced with "zawrs"
> -- "Zfa" should be replaced with "zfa"
> -- "Zfh" should be replaced with "zfh"
> -- "Zfhmin" should be replaced with "zfhmin"
> -- "Zve32f" should be replaced with "zve32f"
> -- "Zve64f" should be replaced with "zve64f"
> -- "Zve64d" should be replaced with "zve64d"
> -
> Block device options
> ''''''''''''''''''''
>
