On Sun, 2011-03-06 at 18:38 -0800, Eric Rannaud wrote: > There are many ways to design a MMU, so some restrictions on scope and > features are likely welcome.
I'd do it this way, but the applicant or you can disagree as long as it works great. The main design goals are to use little FPGA resources, avoid complex logic that would reduce the system clock frequency, and have no impact on performance when the MMU is disabled and a minimal impact when it is enabled. * MMU can be completely disabled, for initial TLB loading and backwards compatibility * Separate instruction and data TLBs * Virtual indexes and physical tags * TLBs running concurrently in the CPU pipeline with the I and D caches, with one cycle latency * TLB storage implemented on FPGA block RAM, enabling a large number of entries to be stored efficiently * Thanks to this large number of entries, we can assume we have a low rate of minor TLB misses, and we handle said misses entirely in software (no hardware-managed system memory backing of the TLB). S. _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
