On Mon, 2011-03-07 at 16:02 +0100, Wesley W. Terpstra wrote:
> When you say in verilog
> always (@posedge clk)
> foo <= a*b;
> then foo has to be updated with the result of the product on each clk edge.
Yes, but in some cases, a synthesizer that supports retiming is able to
push extra registers connected to the operands or the result into the
multiplier macro.
Multipliers composed of several smaller multiplier blocks and adders in
order to handle large operands are possible to infer as well. For
example, this is a valid way to infer a 2-stage pipelined multiplier
with Xst, even if the operands are too large for a single hard
multiplier:
always @(posedge clk) begin
foo <= a*b;
bar <= foo; /* foo is not used anywhere else */
end
Btw, Xilinx DSP48 blocks even contain features to do this kind of things
efficiently:
* built-in registers (with individually accessible clock enable signals)
* built-in adder
* dedicated routing for fast cascading of several blocks
which means the whole LM32 multiplier could be implemented solely with
DSP48 blocks and no general purpose logic. When I tried, Xst (it was
still 11.x) failed to infer that structure, but I guess this would work
with more beefy software like Synplify or maybe even more recent
versions of Xst.
S.
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