Ed Leckie wrote: > Have you looked into using a voltage supervisor to connect to VPEN > pin rather than the 3.3V VCC?
We're having somethign similar in mind to try next: replace the reset chip that's currently being supplied from 3V3 with one that's being supplied from DC input. The underlying theory is that the FPGA core or I/O may lose power quicker than the NOR does. Thus, the FPGA may send out random junk and every once in a while, this junk would happen to be a valid write command. Furthermore, we assume that holding the NOR chip in reset will indeed prevent it from responding to such commands. The reset circuit currently in M1rc3 already handles the power up case, but will not intervene when 3V3 drops more slowly than some other rail. If we hook the reset circuit to DC in, then we're guaranteed that it sees any major drop in the supply voltage long before anything else does. - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
