Hi,
On Sun, 20 Nov 2011 06:07:44 -0300, Werner Almesberger wrote:
So it does indeed seem that the sample clock is running a bit
fast for some reason.
Try sampling 1/4 bit time later?
diff --git a/cores/softusb/rtl/softusb_rx.v
b/cores/softusb/rtl/softusb_rx.v
index 25e1f67..96b6af9 100644
--- a/cores/softusb/rtl/softusb_rx.v
+++ b/cores/softusb/rtl/softusb_rx.v
@@ -121,7 +121,7 @@ always @(posedge usb_clk) begin
dpll_counter <= 5'd0;
else
dpll_counter <= dpll_counter + 5'd1;
- dpll_ce <= low_speed ? (dpll_counter == 5'd13) :
(transition|(dpll_counter[1:0] == 2'd3));
+ dpll_ce <= low_speed ? (dpll_counter == 5'd13) :
(dpll_counter[1:0] == 2'd0);
end
end
(totally untested, I'm still traveling and I don't even have ISE on my
netbook)
Cheers,
Sebastien
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