Yann Sionneau wrote:
> Phase 2 was "allow MMU to generate a CPU exception upon a page fault".

Very good !

One thing that we'll need is a way to track a page's "dirty"
status. There are two ways to do this:

1) have a "dirty" bit (in this case in the TLB) the gateware sets,
   or

2) initially make the page read-only and make the page fault
   handler turn it read-write on the first write fault.

Since we need read-only pages anyway, perhaps it's best to use
the second approach first and then consider whether the first
approach could help to accelerate things.

As far as I can tell, you haven't implemented dirty bits or
page access permissions yet. Do you foresee any difficulties ?

> ITLB will be very similar to DTLB, but it will be significantly harder
> to debug since it touches the execution flow: if the ITLB screws up, the
> CPU will jump to execute some random instructions in the SDRAM :/

Having the nicely debugged DTLB to start from will certainly
help with this ;-)

- Werner
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