On 07/12/2012 07:28 PM, Pierre BARRE wrote:
What do you propose ?
Modern FPGAs have dedicated structures called carry chains that accelerate arithmetic operations like additions and subtractions. The synthesizer uses them automatically when it encounters + and - operators in the Verilog/VHDL source.
Custom logic will most likely be slower and less efficient. A quick web search for "carry chain" will give you some reading material.
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