Making some platform dependent code conditional on their platform.
--
Robert Jordens.
From b7328846c4c77c7cc136aee9edbf1e7b851e84ff Mon Sep 17 00:00:00 2001
From: Robert Jordens <jord...@gmail.com>
Date: Sun, 10 Nov 2013 02:03:58 -0700
Subject: [PATCH 03/12] make.py: make a bit more generic
if parts of the soc are not available or not enables on a platform, do
not use their verilog cores.
Signed-off-by: Robert Jordens <jord...@gmail.com>
---
make.py | 34 ++++++++++++++++++++++------------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/make.py b/make.py
index fc8548f..fd0f4d2 100755
--- a/make.py
+++ b/make.py
@@ -12,14 +12,23 @@ def build(platform_name, build_bitstream, build_header, csr_csv_filename, *soc_a
platform_module = importlib.import_module("mibuild.platforms."+platform_name)
platform = platform_module.Platform()
soc = top.SoC(platform, platform_name, *soc_args, **soc_kwargs)
-
- platform.add_platform_command("""
+
+ if platform_name in ("mixxeo", "m1"):
+ platform.add_platform_command("""
INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")
+ platform.add_source_dir(os.path.join("verilog", "mxcrg"))
+ elif platform_name == "lx9_microboard":
+ platform.add_platform_command("""
+PIN "BUFG_1.O" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "{clk100}" TNM_NET = "GRPclk100";
+TIMESPEC "TSclk100" = PERIOD "GRPclk100" 10 ns HIGH 50%;
+""", clk100=platform.lookup_request("clk_y3"))
if hasattr(soc, "fb"):
platform.add_platform_command("""
@@ -29,16 +38,17 @@ TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
""", vga_clk=soc.fb.driver.clocking.cd_pix.clk)
- for d in ["mxcrg", "minimac3"]:
- platform.add_source_dir(os.path.join("verilog", d))
- platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
- "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
- "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
- "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
- "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
- "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
- "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
- platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
+ if hasattr(soc, "minimac"):
+ platform.add_source_dir(os.path.join("verilog", "minimac3"))
+ if hasattr(soc, "cpu"):
+ platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
+ "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
+ "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
+ "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
+ "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
+ "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
+ "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
+ platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
if build_bitstream:
build_name = "soc-"+platform_name
--
1.8.3.2
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