improved patches as discussed. On Tue, Dec 3, 2013 at 1:13 PM, Robert Jördens <[email protected]> wrote: > these patches add a few more platforms for mibuild and add a lottle > fix for the lx9 microboard. > > -- > Robert Jordens.
-- Robert Jordens.
From 7a6392c52ec2daeb2eb127aa1296988a57fccbc9 Mon Sep 17 00:00:00 2001 From: Robert Jordens <[email protected]> Date: Tue, 3 Dec 2013 14:12:40 -0700 Subject: [PATCH] fhdl.size: rename to bitcontainer --- doc/api.rst | 4 +- migen/fhdl/bitcontainer.py | 202 +++++++++++++++++++++++++++++++++++++++++++++ migen/fhdl/size.py | 202 --------------------------------------------- migen/fhdl/specials.py | 2 +- migen/fhdl/std.py | 2 +- migen/fhdl/structure.py | 4 +- migen/fhdl/tools.py | 2 +- migen/fhdl/verilog.py | 2 +- migen/genlib/cdc.py | 2 +- 9 files changed, 211 insertions(+), 211 deletions(-) create mode 100644 migen/fhdl/bitcontainer.py delete mode 100644 migen/fhdl/size.py diff --git a/doc/api.rst b/doc/api.rst index d49b9b7..1181773 100644 --- a/doc/api.rst +++ b/doc/api.rst @@ -8,10 +8,10 @@ migen API Documentation :members: :show-inheritance: -:mod:`fhdl.size` Module +:mod:`fhdl.bitcontainer` Module ------------------------------ -.. automodule:: migen.fhdl.size +.. automodule:: migen.fhdl.bitcontainer :members: :show-inheritance: diff --git a/migen/fhdl/bitcontainer.py b/migen/fhdl/bitcontainer.py new file mode 100644 index 0000000..345c9c5 --- /dev/null +++ b/migen/fhdl/bitcontainer.py @@ -0,0 +1,202 @@ +from migen.fhdl import structure as f + +def log2_int(n, need_pow2=True): + l = 1 + r = 0 + while l < n: + l *= 2 + r += 1 + if need_pow2 and l != n: + raise ValueError("Not a power of 2") + return r + +def bits_for(n, require_sign_bit=False): + if n > 0: + r = log2_int(n + 1, False) + else: + require_sign_bit = True + r = log2_int(-n, False) + if require_sign_bit: + r += 1 + return r + +def value_bits_sign(v): + if isinstance(v, bool): + return 1, False + elif isinstance(v, int): + return bits_for(v), v < 0 + elif isinstance(v, f.Signal): + return v.nbits, v.signed + elif isinstance(v, (f.ClockSignal, f.ResetSignal)): + return 1, False + elif isinstance(v, f._Operator): + obs = list(map(value_bits_sign, v.operands)) + if v.op == "+" or v.op == "-": + if not obs[0][1] and not obs[1][1]: + # both operands unsigned + return max(obs[0][0], obs[1][0]) + 1, False + elif obs[0][1] and obs[1][1]: + # both operands signed + return max(obs[0][0], obs[1][0]) + 1, True + elif not obs[0][1] and obs[1][1]: + # first operand unsigned (add sign bit), second operand signed + return max(obs[0][0] + 1, obs[1][0]) + 1, True + else: + # first signed, second operand unsigned (add sign bit) + return max(obs[0][0], obs[1][0] + 1) + 1, True + elif v.op == "*": + if not obs[0][1] and not obs[1][1]: + # both operands unsigned + return obs[0][0] + obs[1][0] + elif obs[0][1] and obs[1][1]: + # both operands signed + return obs[0][0] + obs[1][0] - 1 + else: + # one operand signed, the other unsigned (add sign bit) + return obs[0][0] + obs[1][0] + 1 - 1 + elif v.op == "<<<": + if obs[1][1]: + extra = 2**(obs[1][0] - 1) - 1 + else: + extra = 2**obs[1][0] - 1 + return obs[0][0] + extra, obs[0][1] + elif v.op == ">>>": + if obs[1][1]: + extra = 2**(obs[1][0] - 1) + else: + extra = 0 + return obs[0][0] + extra, obs[0][1] + elif v.op == "&" or v.op == "^" or v.op == "|": + if not obs[0][1] and not obs[1][1]: + # both operands unsigned + return max(obs[0][0], obs[1][0]), False + elif obs[0][1] and obs[1][1]: + # both operands signed + return max(obs[0][0], obs[1][0]), True + elif not obs[0][1] and obs[1][1]: + # first operand unsigned (add sign bit), second operand signed + return max(obs[0][0] + 1, obs[1][0]), True + else: + # first signed, second operand unsigned (add sign bit) + return max(obs[0][0], obs[1][0] + 1), True + elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \ + or v.op == ">" or v.op == ">=": + return 1, False + elif v.op == "~": + return obs[0] + else: + raise TypeError + elif isinstance(v, f._Slice): + return v.stop - v.start, value_bits_sign(v.value)[1] + elif isinstance(v, f.Cat): + return sum(value_bits_sign(sv)[0] for sv in v.l), False + elif isinstance(v, f.Replicate): + return (value_bits_sign(v.v)[0])*v.n, False + elif isinstance(v, f._ArrayProxy): + bsc = map(value_bits_sign, v.choices) + return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc) + else: + raise TypeError("Can not calculate bit length of {} {}".format( + type(v), v)) + +def flen(v): + """Bit length of an expression + + Parameters + ---------- + v : int, bool or Value + + Returns + ------- + int + Number of bits required to store `v` or available in `v` + + Examples + -------- + >>> flen(f.Signal(8)) + 8 + >>> flen(0xaa) + 8 + """ + return value_bits_sign(v)[0] + +def fiter(v): + """Bit iterator + + Parameters + ---------- + v : int, bool or Value + + Returns + ------- + iter + Iterator over the bits in `v` + + Examples + -------- + >>> list(fiter(f.Signal(2))) #doctest: +ELLIPSIS + [<migen.fhdl.structure._Slice object at 0x...>, <migen.fhdl.structure._Slice object at 0x...>] + >>> list(fiter(4)) + [0, 0, 1] + """ + if isinstance(v, (bool, int)): + return ((v >> i) & 1 for i in range(bits_for(v))) + elif isinstance(v, f.Value): + return (v[i] for i in range(flen(v))) + else: + raise TypeError("Can not bit-iterate {} {}".format(type(v), v)) + +def fslice(v, s): + """Bit slice + + Parameters + ---------- + v : int, bool or Value + s : slice or int + + Returns + ------- + int or Value + Expression for the slice `s` of `v`. + + Examples + -------- + >>> fslice(f.Signal(2), 1) #doctest: +ELLIPSIS + <migen.fhdl.structure._Slice object at 0x...> + >>> bin(fslice(0b1101, slice(1, None, 2))) + '0b10' + >>> fslice(-1, slice(0, 4)) + 1 + >>> fslice(-7, slice(None)) + 9 + """ + if isinstance(v, (bool, int)): + if isinstance(s, int): + s = slice(s) + idx = range(*s.indices(bits_for(v))) + return sum(((v >> i) & 1) << j for j, i in enumerate(idx)) + elif isinstance(v, f.Value): + return v[s] + else: + raise TypeError("Can not bit-slice {} {}".format(type(v), v)) + +def freversed(v): + """Bit reverse + + Parameters + ---------- + v : int, bool or Value + + Returns + ------- + int or Value + Expression containing the bit reversed input. + + Examples + -------- + >>> freversed(f.Signal(2)) #doctest: +ELLIPSIS + <migen.fhdl.structure.Cat object at 0x...> + >>> bin(freversed(0b1011)) + '0b1101' + """ + return fslice(v, slice(None, None, -1)) diff --git a/migen/fhdl/size.py b/migen/fhdl/size.py deleted file mode 100644 index 345c9c5..0000000 --- a/migen/fhdl/size.py +++ /dev/null @@ -1,202 +0,0 @@ -from migen.fhdl import structure as f - -def log2_int(n, need_pow2=True): - l = 1 - r = 0 - while l < n: - l *= 2 - r += 1 - if need_pow2 and l != n: - raise ValueError("Not a power of 2") - return r - -def bits_for(n, require_sign_bit=False): - if n > 0: - r = log2_int(n + 1, False) - else: - require_sign_bit = True - r = log2_int(-n, False) - if require_sign_bit: - r += 1 - return r - -def value_bits_sign(v): - if isinstance(v, bool): - return 1, False - elif isinstance(v, int): - return bits_for(v), v < 0 - elif isinstance(v, f.Signal): - return v.nbits, v.signed - elif isinstance(v, (f.ClockSignal, f.ResetSignal)): - return 1, False - elif isinstance(v, f._Operator): - obs = list(map(value_bits_sign, v.operands)) - if v.op == "+" or v.op == "-": - if not obs[0][1] and not obs[1][1]: - # both operands unsigned - return max(obs[0][0], obs[1][0]) + 1, False - elif obs[0][1] and obs[1][1]: - # both operands signed - return max(obs[0][0], obs[1][0]) + 1, True - elif not obs[0][1] and obs[1][1]: - # first operand unsigned (add sign bit), second operand signed - return max(obs[0][0] + 1, obs[1][0]) + 1, True - else: - # first signed, second operand unsigned (add sign bit) - return max(obs[0][0], obs[1][0] + 1) + 1, True - elif v.op == "*": - if not obs[0][1] and not obs[1][1]: - # both operands unsigned - return obs[0][0] + obs[1][0] - elif obs[0][1] and obs[1][1]: - # both operands signed - return obs[0][0] + obs[1][0] - 1 - else: - # one operand signed, the other unsigned (add sign bit) - return obs[0][0] + obs[1][0] + 1 - 1 - elif v.op == "<<<": - if obs[1][1]: - extra = 2**(obs[1][0] - 1) - 1 - else: - extra = 2**obs[1][0] - 1 - return obs[0][0] + extra, obs[0][1] - elif v.op == ">>>": - if obs[1][1]: - extra = 2**(obs[1][0] - 1) - else: - extra = 0 - return obs[0][0] + extra, obs[0][1] - elif v.op == "&" or v.op == "^" or v.op == "|": - if not obs[0][1] and not obs[1][1]: - # both operands unsigned - return max(obs[0][0], obs[1][0]), False - elif obs[0][1] and obs[1][1]: - # both operands signed - return max(obs[0][0], obs[1][0]), True - elif not obs[0][1] and obs[1][1]: - # first operand unsigned (add sign bit), second operand signed - return max(obs[0][0] + 1, obs[1][0]), True - else: - # first signed, second operand unsigned (add sign bit) - return max(obs[0][0], obs[1][0] + 1), True - elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \ - or v.op == ">" or v.op == ">=": - return 1, False - elif v.op == "~": - return obs[0] - else: - raise TypeError - elif isinstance(v, f._Slice): - return v.stop - v.start, value_bits_sign(v.value)[1] - elif isinstance(v, f.Cat): - return sum(value_bits_sign(sv)[0] for sv in v.l), False - elif isinstance(v, f.Replicate): - return (value_bits_sign(v.v)[0])*v.n, False - elif isinstance(v, f._ArrayProxy): - bsc = map(value_bits_sign, v.choices) - return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc) - else: - raise TypeError("Can not calculate bit length of {} {}".format( - type(v), v)) - -def flen(v): - """Bit length of an expression - - Parameters - ---------- - v : int, bool or Value - - Returns - ------- - int - Number of bits required to store `v` or available in `v` - - Examples - -------- - >>> flen(f.Signal(8)) - 8 - >>> flen(0xaa) - 8 - """ - return value_bits_sign(v)[0] - -def fiter(v): - """Bit iterator - - Parameters - ---------- - v : int, bool or Value - - Returns - ------- - iter - Iterator over the bits in `v` - - Examples - -------- - >>> list(fiter(f.Signal(2))) #doctest: +ELLIPSIS - [<migen.fhdl.structure._Slice object at 0x...>, <migen.fhdl.structure._Slice object at 0x...>] - >>> list(fiter(4)) - [0, 0, 1] - """ - if isinstance(v, (bool, int)): - return ((v >> i) & 1 for i in range(bits_for(v))) - elif isinstance(v, f.Value): - return (v[i] for i in range(flen(v))) - else: - raise TypeError("Can not bit-iterate {} {}".format(type(v), v)) - -def fslice(v, s): - """Bit slice - - Parameters - ---------- - v : int, bool or Value - s : slice or int - - Returns - ------- - int or Value - Expression for the slice `s` of `v`. - - Examples - -------- - >>> fslice(f.Signal(2), 1) #doctest: +ELLIPSIS - <migen.fhdl.structure._Slice object at 0x...> - >>> bin(fslice(0b1101, slice(1, None, 2))) - '0b10' - >>> fslice(-1, slice(0, 4)) - 1 - >>> fslice(-7, slice(None)) - 9 - """ - if isinstance(v, (bool, int)): - if isinstance(s, int): - s = slice(s) - idx = range(*s.indices(bits_for(v))) - return sum(((v >> i) & 1) << j for j, i in enumerate(idx)) - elif isinstance(v, f.Value): - return v[s] - else: - raise TypeError("Can not bit-slice {} {}".format(type(v), v)) - -def freversed(v): - """Bit reverse - - Parameters - ---------- - v : int, bool or Value - - Returns - ------- - int or Value - Expression containing the bit reversed input. - - Examples - -------- - >>> freversed(f.Signal(2)) #doctest: +ELLIPSIS - <migen.fhdl.structure.Cat object at 0x...> - >>> bin(freversed(0b1011)) - '0b1101' - """ - return fslice(v, slice(None, None, -1)) diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index ad11f57..ae0a2e6 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -1,7 +1,7 @@ from operator import itemgetter from migen.fhdl.structure import * -from migen.fhdl.size import bits_for, value_bits_sign +from migen.fhdl.bitcontainer import bits_for, value_bits_sign from migen.fhdl.tools import * from migen.fhdl.tracer import get_obj_var_name from migen.fhdl.verilog import _printexpr as verilog_printexpr diff --git a/migen/fhdl/std.py b/migen/fhdl/std.py index b9ec729..2007ff3 100644 --- a/migen/fhdl/std.py +++ b/migen/fhdl/std.py @@ -1,5 +1,5 @@ from migen.fhdl.structure import * from migen.fhdl.module import Module from migen.fhdl.specials import TSTriple, Instance, Memory -from migen.fhdl.size import log2_int, bits_for, flen, fiter, fslice, freversed +from migen.fhdl.bitcontainer import log2_int, bits_for, flen, fiter, fslice, freversed from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index aba747b..9b31e69 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -79,7 +79,7 @@ class Value(HUID): def __getitem__(self, key): - from migen.fhdl.size import flen + from migen.fhdl.bitcontainer import flen if isinstance(key, int): if key < 0: @@ -242,7 +242,7 @@ class Signal(Value): related : Signal or None """ def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None): - from migen.fhdl.size import bits_for + from migen.fhdl.bitcontainer import bits_for Value.__init__(self) diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py index b25280b..00c9932 100644 --- a/migen/fhdl/tools.py +++ b/migen/fhdl/tools.py @@ -1,7 +1,7 @@ from migen.fhdl.structure import * from migen.fhdl.structure import _Slice, _Assign from migen.fhdl.visit import NodeVisitor, NodeTransformer -from migen.fhdl.size import value_bits_sign +from migen.fhdl.bitcontainer import value_bits_sign from migen.util.misc import flat_iteration class _SignalLister(NodeVisitor): diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 10bd7e3..fc56f78 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -4,7 +4,7 @@ from operator import itemgetter from migen.fhdl.structure import * from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment from migen.fhdl.tools import * -from migen.fhdl.size import bits_for, flen +from migen.fhdl.bitcontainer import bits_for, flen from migen.fhdl.namer import Namespace, build_namespace def _printsig(ns, s): diff --git a/migen/genlib/cdc.py b/migen/genlib/cdc.py index 773c7b2..9cdca4a 100644 --- a/migen/genlib/cdc.py +++ b/migen/genlib/cdc.py @@ -1,5 +1,5 @@ from migen.fhdl.std import * -from migen.fhdl.size import value_bits_sign +from migen.fhdl.bitcontainer import value_bits_sign from migen.fhdl.specials import Special from migen.fhdl.tools import list_signals -- 1.8.3.2
From 46af4072e432135edd8935675f939aaf222401bc Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq <[email protected]> Date: Tue, 17 Sep 2013 18:14:41 +0200 Subject: [PATCH 1/8] lx9 fixups --- mibuild/platforms/lx9_microboard.py | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index 955aea5..c3195e0 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -45,6 +45,11 @@ _io = [ Subsignal("d", Pins("H12 G13 E16 E18 K12 K13 F17 F18")), IOStandard("LVCMOS33")), + ("pmod_diff", 0, + Subsignal("io", Pins("F15 C17 F14 D17 H12 E16 K12 F17")), + Subsignal("iob", Pins("F16 C18 G14 D18 G13 E18 K13 F18")), + IOStandard("LVCMOS33")), + ("serial", 0, Subsignal("tx", Pins("T7"), Misc("SLEW=SLOW")), Subsignal("rx", Pins("R7"), Misc("PULLUP")), @@ -73,7 +78,7 @@ _io = [ IOStandard("MOBILE_DDR")), # Nat Semi DP83848J 10/100 Ethernet PHY - # pull-ups on rx_data set phy addr to 11110b + # pull-ups on col and rx_data set phy addr to 11111b # and prevent isolate mode (addr 00000b) ("eth_clocks", 0, Subsignal("rx", Pins("L15")), @@ -81,14 +86,14 @@ _io = [ IOStandard("LVCMOS33")), ("eth", 0, - Subsignal("col", Pins("M18"), Misc("PULLDOWN")), + Subsignal("col", Pins("M18"), Misc("PULLUP")), Subsignal("crs", Pins("N17"), Misc("PULLDOWN")), - Subsignal("mdc", Pins("M16")), - Subsignal("mdio", Pins("L18")), + Subsignal("mdc", Pins("M16"), Misc("PULLDOWN")), + Subsignal("mdio", Pins("L18"), Misc("PULLUP")), # 1k5 ext PULLUP Subsignal("rst_n", Pins("T18"), Misc("TIG")), Subsignal("rx_data", Pins("T17 N16 N15 P18"), Misc("PULLUP")), - Subsignal("dv", Pins("P17")), - Subsignal("rx_er", Pins("N18")), + Subsignal("dv", Pins("P17"), Misc("PULLDOWN")), # MII + Subsignal("rx_er", Pins("N18"), Misc("PULLUP")), # auto MDIX Subsignal("tx_data", Pins("K18 K17 J18 J16")), Subsignal("tx_en", Pins("L17")), Subsignal("tx_er", Pins("L16")), # NC! @@ -99,13 +104,21 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io, - lambda p: CRG_SE(p, "clk_y3", "user_btn", 10.)) + lambda p: CRG_SE(p, "clk_y3", "user_btn")) self.add_platform_command(""" CONFIG VCCAUX = "3.3"; """) def do_finalize(self, fragment): try: + self.add_platform_command(""" +NET "{clk_y3}" TNM_NET = "GRPclky3"; +TIMESPEC "TSclky3" = PERIOD "GRPclky3" 10 ns HIGH 50%; +""", clk_y3=self.lookup_request("clk_y3")) + except ConstraintError: + pass + + try: eth_clocks = self.lookup_request("eth_clocks") self.add_platform_command(""" NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; -- 1.8.3.2
From 0f1f5827a74fd8f1b192febfab4577bcea955e53 Mon Sep 17 00:00:00 2001 From: Robert Jordens <[email protected]> Date: Thu, 4 Jul 2013 01:06:55 -0600 Subject: [PATCH 2/8] add initial ztex_115d platform --- mibuild/platforms/ztex_115d.py | 112 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 mibuild/platforms/ztex_115d.py diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py new file mode 100644 index 0000000..8889b1d --- /dev/null +++ b/mibuild/platforms/ztex_115d.py @@ -0,0 +1,112 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE + +_io = [ + ("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")), + ("clk_if", 0, Pins("K20"), IOStandard("LVCMOS33")), + ("rst", 0, Pins("A18")), + # PROG_B and DONE: AA1 U16 + + ("fx2", 0, + Subsignal("sloe", Pins("U15"), Drive(12)), # M1 + Subsignal("slrd", Pins("N22"), Drive(12)), + Subsignal("slwr", Pins("M22"), Drive(12)), + Subsignal("pktend", Pins("AB5"), Drive(12)), # CSO + Subsignal("fifoadr", Pins("W17 Y18"), Drive(12)), # CCLK M0 + Subsignal("cont", Pins("G20")), + Subsignal("fd", Pins("Y17 V13 W13 AA8 AB8 W6 Y6 Y9 " + "V21 V22 U20 U22 R20 R22 P18 P19")), + Subsignal("flag", Pins("F20 F19 F18 AB17")), # - - - CSI/MOSI + Subsignal("rdy25", Pins("M21 K21 K22 J21")), + Subsignal("ctl35", Pins("D19 E20 N20")), + Subsignal("int45", Pins("C18 V17")), + Subsignal("pc", Pins("G20 T10 V5 AB9 G19 H20 H19 H18")), + # - DOUT/BUSY INIT_B RDWR_B DO CS CLK DI + IOStandard("LVCMOS33")), + + ("mm", 0, + Subsignal("a", Pins("M20 M19 M18 N19 T19 T21 T22 R19 ", + "P20 P21 P22 J22 H21 H22 G22 F21")), + Subsignal("d", Pins("D20 C20 C19 B21 B20 J19 K19 L19"), Drive(2)), + Subsignal("wr_n", Pins("C22")), + Subsignal("rd_n", Pins("D21")), + Subsignal("psen_n", Pins("D22")), + IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("B22"), Misc("SLEW=QUIETIO")), + Subsignal("rx", Pins("A21"), Misc("PULLDOWN")), + IOStandard("LVCMOS33")), + + ("ddram_clock", 0, + Subsignal("p", Pins("F2"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("n", Pins("F1"), Misc("OUT_TERM=UNTUNED_50")), + IOStandard("SSTL18_II")), + + ("ddram", 0, + Subsignal("dqs", Pins("L3 T2"), IOStandard("SSTL18_II"), # DIFF_ + Misc("IN_TERM=NONE")), + Subsignal("dqs_n", Pins("L1 T1"), IOStandard("SSTL18_II"), # DIFF_ + Misc("IN_TERM=NONE")), + Subsignal("dm", Pins("H1 H2"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("dq", Pins("M1 M2 J1 K2 J3 K1 N3 N1 " + "U1 U3 P1 R3 P2 R1 V2 V1"), Misc("IN_TERM=NONE")), + Subsignal("ras_n", Pins("N4"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("cas_n", Pins("P3"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("a", Pins("M5 K6 B1 J4 L4 K3 M4 K5 G3 G1 K4 C3 C1"), + Misc("OUT_TERM=UNTUNED_50")), + Subsignal("ba", Pins("E3 E1 D1"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("cke", Pins("J6"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("cs_n", Pins("H6")), # NC! + Subsignal("odt", Pins("M3"), Misc("OUT_TERM=UNTUNED_50")), + Subsignal("we_n", Pins("D2")), + Subsignal("rzq", Pins("AA2")), + Subsignal("zio", Pins("Y2")), + IOStandard("SSTL18_II")), + + ("i2c", 0, + Subsignal("scl", Pins("F22")), + Subsignal("sda", Pins("E22")), + IOStandard("LVCMOS33")), + + ("sd", 0, + Subsignal("sck", Pins("H11")), + Subsignal("d3", Pins("H14")), + Subsignal("d", Pins("P10")), + Subsignal("d1", Pins("T18")), + Subsignal("d2", Pins("R17")), + Subsignal("cmd", Pins("H13")), + IOStandard("LVCMOS33")), + +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io, + lambda p: CRG_SE(p, "clk_if", "rst")) + self.add_platform_command(""" +CONFIG VCCAUX = "2.5"; +""") + + def do_finalize(self, fragment): + try: + self.add_platform_command(""" +NET "{clk_if}" TNM_NET = "GRPclkif"; +TIMESPEC "TSclkif" = PERIOD "GRPclkif" 20 ns HIGH 50%; +""", clk_if=self.lookup_request("clk_if")) + except ConstraintError: + pass + + try: + clk_if = self.lookup_request("clk_if") + clk_fx = self.lookup_request("clk_fx") + self.add_platform_command(""" +NET "{clk_if}" TNM_NET = "GRPclk_if"; +NET "{clk_fx}" TNM_NET = "GRPclk_fx"; +TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%; +TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%; +TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY; +TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY; +""", clk_if=clk_if, clk_fx=clk_fx) + except ContraintError: + pass -- 1.8.3.2
From 2eba8c9586848c3b0869883694d7574a492d1322 Mon Sep 17 00:00:00 2001 From: Robert Jordens <[email protected]> Date: Tue, 16 Jul 2013 23:23:40 -0600 Subject: [PATCH 3/8] add zedboard platform --- mibuild/platforms/zedboard.py | 151 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 mibuild/platforms/zedboard.py diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py new file mode 100644 index 0000000..2d99fd0 --- /dev/null +++ b/mibuild/platforms/zedboard.py @@ -0,0 +1,151 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE + +# Bank 34 and 35 voltage depend on J18 jumper setting +_io = [ + ("clk100", 0, Pins("Y9"), IOStandard("LVCMOS33")), + + ("user_btn", 0, Pins("P16"), IOStandard("LVCMOS18")), # center + ("user_btn", 1, Pins("R16"), IOStandard("LVCMOS18")), # down + ("user_btn", 2, Pins("N15"), IOStandard("LVCMOS18")), # left + ("user_btn", 3, Pins("R18"), IOStandard("LVCMOS18")), # right + ("user_btn", 4, Pins("T18"), IOStandard("LVCMOS18")), # up + + ("user_sw", 0, Pins("F22"), IOStandard("LVCMOS18")), + ("user_sw", 1, Pins("G22"), IOStandard("LVCMOS18")), + ("user_sw", 2, Pins("H22"), IOStandard("LVCMOS18")), + ("user_sw", 3, Pins("F21"), IOStandard("LVCMOS18")), + ("user_sw", 4, Pins("H19"), IOStandard("LVCMOS18")), + ("user_sw", 5, Pins("H18"), IOStandard("LVCMOS18")), + ("user_sw", 6, Pins("H17"), IOStandard("LVCMOS18")), + ("user_sw", 7, Pins("M15"), IOStandard("LVCMOS18")), + + ("user_led", 0, Pins("T22"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("T21"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("U22"), IOStandard("LVCMOS33")), + ("user_led", 3, Pins("U21"), IOStandard("LVCMOS33")), + ("user_led", 4, Pins("V22"), IOStandard("LVCMOS33")), + ("user_led", 5, Pins("W22"), IOStandard("LVCMOS33")), + ("user_led", 6, Pins("U19"), IOStandard("LVCMOS33")), + ("user_led", 7, Pins("U14"), IOStandard("LVCMOS33")), + + # A + ("pmod", 0, Pins("Y11 AA11 Y10 AA9 AB11 AB10 AB9 AA8"), + IOStandard("LVCMOS33")), + # B + ("pmod", 1, Pins("W12 W11 V10 W8 V12 W10 V9 V8"), + IOStandard("LVCMOS33")), + # C + ("pmod", 2, + Subsignal("n", Pins("AB6 AA4 T6 U4")), + Subsignal("p", Pins("AB7 Y4 R6 T4")), + IOStandard("LVCMOS33")), + # D + ("pmod", 3, + Subsignal("n", Pins("W7 V4 W5 U5")), + Subsignal("p", Pins("V7 V5 W6 U6")), + IOStandard("LVCMOS33")), + + ("audio", 0, + Subsignal("adr", Pins("AB1 Y5")), + Subsignal("gpio", Pins("Y8 AA7 AA6 Y6")), + Subsignal("mclk", Pins("AB2")), + Subsignal("sck", Pins("AB4")), + Subsignal("sda", Pins("AB5")), + IOStandard("LVCMOS33")), + + ("oled", 0, + Subsignal("dc", Pins("U10")), + Subsignal("res", Pins("U9")), + Subsignal("sclk", Pins("AB12")), + Subsignal("sdin", Pins("AA12")), + Subsignal("vbat", Pins("U11")), + Subsignal("vdd", Pins("U12")), + IOStandard("LVCMOS33")), + + ("hdmi", 0, + Subsignal("clk", Pins("W18")), + Subsignal("d", Pins( + "Y13 AA13 AA14 Y14 AB15 AB16 AA16 AB17 " + "AA17 Y15 W13 W15 V15 U17 V14 V13")), + Subsignal("de", Pins("U16")), + Subsignal("hsync", Pins("V17")), + Subsignal("vsync", Pins("W17")), + Subsignal("int", Pins("W16")), + Subsignal("scl", Pins("AA18")), + Subsignal("sda", Pins("Y16")), + Subsignal("spdif", Pins("U15")), + Subsignal("spdifo", Pins("Y18")), + IOStandard("LVCMOS33")), + + ("netic16", 0, + Subsignal("w20", Pins("W20")), + Subsignal("w21", Pins("W21")), + IOStandard("LVCMOS33")), + + ("vga", 0, + Subsignal("r", Pins("V20 U20 V19 V18")), + Subsignal("g", Pins("AB22 AA22 AB21 AA21")), + Subsignal("b", Pins("Y21 Y20 AB20 AB19")), + Subsignal("hsync_n", Pins("AA19")), + Subsignal("vsync_n", Pins("Y19")), + IOStandard("LVCMOS33")), + + ("usb_otg", 0, + Subsignal("vbusoc", Pins("L16")), + Subsignal("reset_n", Pins("G17")), + IOStandard("LVCMOS18")), + + ("pudc_b", 0, Pins("K16"), IOStandard("LVCMOS18")), + + ("xadc", 0, + Subsignal("gio", Pins("H15 R15 K15 J15")), + Subsignal("ad0_n", Pins("E16")), + Subsignal("ad0_p", Pins("F16")), + Subsignal("ad8_n", Pins("D17")), + Subsignal("ad8_p", Pins("D16")), + IOStandard("LVCMOS18")), + + ("fmc_clocks", 0, + Subsignal("clk0_n", Pins("L19")), + Subsignal("clk0_p", Pins("L18")), + Subsignal("clk1_n", Pins("C19")), + Subsignal("clk1_p", Pins("D18")), + IOStandard("LVCMOS18")), + + ("fmc", 0, + Subsignal("scl", Pins("R7")), + Subsignal("sda", Pins("U7")), + + Subsignal("prsnt", Pins("AB14")), + + # 0, 1, 17, 18 can be clock signals + Subsignal("la_n", Pins( + "M20 N20 P18 P22 M22 K18 L22 T17 " + "J22 R21 T19 N18 P21 M17 K20 J17 " + "K21 B20 C20 G16 G21 E20 F19 D15 " + "A19 C22 E18 D21 A17 C18 B15 B17 " + "A22 B22")), + Subsignal("la_p", Pins( + "M19 N19 P17 N22 M21 J18 L21 T16 " + "J21 R20 R19 N17 P20 L17 K19 J16 " + "J20 B19 D20 G15 G20 E19 G19 E15 " + "A18 D22 F18 E21 A16 C17 C15 B16 " + "A21 B21")), + IOStandard("LVCMOS18")), +] + + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io, + lambda p: CRG_SE(p, "clk100", None)) + + def do_finalize(self, fragment): + try: + self.add_platform_command(""" +NET "{clk100}" TNM_NET = "GRPclk100"; +TIMESPEC "TSclk100" = PERIOD "GRPclk100" 10 ns HIGH 50%; +""", clk100=self.lookup_request("clk100")) + except ConstraintError: + pass -- 1.8.3.2
From ffbdaaf1db43af7e0977c482c7aeda1bfd90bfe2 Mon Sep 17 00:00:00 2001 From: Robert Jordens <[email protected]> Date: Sat, 16 Nov 2013 03:22:09 -0700 Subject: [PATCH 4/8] usrp_b100 platform --- mibuild/platforms/usrp_b100.py | 154 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 mibuild/platforms/usrp_b100.py diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py new file mode 100644 index 0000000..dc040c4 --- /dev/null +++ b/mibuild/platforms/usrp_b100.py @@ -0,0 +1,154 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_DS + +_io = [ + ("clk64", 0, + Subsignal("p", Pins("R7")), + Subsignal("n", Pins("T7")), + IOStandard("LVDS_33"), + Misc("DIFF_TERM=TRUE"), + ), + + ("pps", 0, Pins("M14"), Misc("TIG")), + ("reset_n", 0, Pins("D5"), Misc("TIG")), + ("codec_reset", 0, Pins("B14")), + # recycles fpga_cfg_cclk for reset from fw + ("ext_reset", 0, Pins("R14")), + + ("i2c", 0, + Subsignal("sda", Pins("T13")), + Subsignal("scl", Pins("R13")), + ), + + ("cgen", 0, + Subsignal("st_ld", Pins("M13")), + Subsignal("st_refmon", Pins("J14")), + Subsignal("st_status", Pins("P6")), + Subsignal("ref_sel", Pins("T2")), + Subsignal("sync_b", Pins("H15")), + ), + + ("fx2_ifclk", 0, Pins("T8")), + ("fx2_gpif", 0, + Subsignal("d", Pins("P8 P9 N9 T9 R9 P11 P13 N12 " + "T3 R3 P5 N6 T6 T5 N8 P7")), + Subsignal("ctl", Pins("M7 M9 M11 P12")), + Subsignal("slwr", Pins("T4")), # rdy0 + Subsignal("slrd", Pins("R5")), # rdy1 + #Subsignal("rdy2", Pins("T10")), + #Subsignal("rdy3", Pins("N11")), + #Subsignal("cs", Pins("P12")), + Subsignal("sloe", Pins("R11")), + Subsignal("pktend", Pins("P10")), + Subsignal("adr", Pins("T11 H16")), + ), + + ("user_led", 0, Pins("P4"), Misc("TIG")), + ("user_led", 1, Pins("N4"), Misc("TIG")), + ("user_led", 2, Pins("R2"), Misc("TIG")), + + ("debug_clk", 0, Pins("K15 K14")), + ("debug", 0, Pins( + "K16 J16 C16 C15 E13 D14 D16 D15 " + "E14 F13 G13 F14 E16 F15 H13 G14 " + "G16 F16 J12 J13 L14 L16 M15 M16 " + "L13 K13 P16 N16 R15 P15 N13 N14")), + + ("adc", 0, + Subsignal("sync", Pins("D10")), + Subsignal("d", Pins("A4 B3 A3 D9 C10 A9 C9 D8 " + "C8 B8 A8 B15")), + ), + ("dac", 0, + Subsignal("blank", Pins("K1")), + Subsignal("sync", Pins("J2")), + Subsignal("d", Pins("J1 H3 J3 G2 H1 N3 M4 R1 " + "P2 P1 M1 N1 M3 L4")), + ), + ("codec_spi", 0, + Subsignal("sclk", Pins("K3")), + Subsignal("sen", Pins("D13")), + Subsignal("mosi", Pins("C13")), + Subsignal("miso", Pins("G4")), + ), + + ("aux_spi", 0, + Subsignal("sen", Pins("C12")), + Subsignal("sclk", Pins("D12")), + Subsignal("miso", Pins("J5")), + ), + ("rx_io", 0, Pins("D7 C6 A6 B6 E9 A7 C7 B10 " + "A10 C11 A11 D11 B12 A12 A14 A13")), + ("tx_io", 0, Pins("K4 L3 L2 F1 F3 G3 E3 E2 " + "E4 F4 D1 E1 D4 D3 C2 C1")), + ("rx_spi", 0, + Subsignal("miso", Pins("E6")), + Subsignal("sen", Pins("B4")), + Subsignal("mosi", Pins("A5")), + Subsignal("sclk", Pins("C5")), + ), + ("tx_spi", 0, + Subsignal("miso", Pins("J4")), + Subsignal("sen", Pins("N2")), + Subsignal("mosi", Pins("L1")), + Subsignal("sclk", Pins("G1")), + ), + + # these are just for information. do not request. + ("mystery_bus", 0, Pins("C4 E7")), + ("fpga_cfg", + Subsignal("din", Pins("T14")), + Subsignal("cclk", Pins("R14")), + Subsignal("init_b", Pins("T12")), + Subsignal("prog_b", Pins("A2")), + Subsignal("done", Pins("T15")), + ), + ("jtag", + Subsignal("tms", Pins("B2")), + Subsignal("tdo", Pins("B16")), + Subsignal("tdi", Pins("B1")), + Subsignal("tck", Pins("A15")), + ), +] + + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io, + lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True)) + + def do_finalize(self, fragment): + try: + self.add_platform_command(""" +NET "{clk64}" TNM_NET = "GRPclk64"; +TIMESPEC "TSclk64" = PERIOD "GRPclk64" 15.625 ns HIGH 50%; +""", clk64=self.lookup_request("clk64")) + except ConstraintError: + pass + + self.add_platform_command(""" +TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; +""") + + try: + ifclk = self.lookup_request("fx2_ifclk") + gpif = self.lookup_request("fx2_gpif") + for i, d in [(gpif.d, "in"), (gpif.d, "out"), + (gpif.ctl, "in"), (gpif.adr, "out"), + (gpif.slwr, "out"), (gpif.sloe, "out"), + (gpif.slrd, "out"), (gpif.pktend, "out")]: + if flen(i) > 1: + q = "(*)" + else: + q = "" + self.add_platform_command(""" +INST "{i}%s" TNM = gpif_net_%s; +""" % (q, d), i=i) + self.add_platform_command(""" +NET "{ifclk}" TNM_NET = "GRPifclk"; +TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%; +TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING; +TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING; +""", ifclk=ifclk) + except ConstraintError: + pass -- 1.8.3.2
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