-------- Original Message --------
Subject: Re: Yosys / EHSM
Date: Wed, 4 Dec 2013 22:01:05 +0100
From: Clifford Wolf <[email protected]>
To: S?bastien Bourdeauducq <[email protected]>
Hi again,
On Wed, Dec 04, 2013 at 07:28:58PM +0100, Clifford Wolf wrote:
> > https://github.com/m-labs/lm32/blob/master/rtl/lm32_dcache.v#L308
> > https://github.com/m-labs/lm32/blob/master/rtl/lm32_load_store_unit.v#L652
>
> ah, ok. (the problem is in line 357 in lm32_dcache.v, btw.)
>
> in both cases it is the same issue: there is code within a generate block
> but not within a "begin:<name> ... end" block. This is of course a bug in
> yosys, the "begin:<name> ... end" block is only mandatory when regs or
> wires are created. I will add that feature now.
it should all be working now. I've also implemented $clog2. The lm32 source
code is now excepted by the Yosys Verilog frontend. I'll download the gcc
port for it tomorrow and see if I'll get the test bench running, then add
it to yosys-bigsim [1].
yours,
- clifford
[1] https://github.com/cliffordwolf/yosys-bigsim
--
"Ampere was the Newton of Electricity."-- James Clerk Maxwell
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