Hello, Sebastien asked me to also post the following to this mailing list. Please CC me in replies as I am not subscribed. (I'm subscribed with mail delivery turned off).
A little bit of background information: I'm trying to include lm32 as one of the testcases in yosys-bigsim, a collection of verilog cores plus test benches used for regression testing in yosys. I have troubles getting the rtl simulation to work properly. The "hello world" example works, but my test program does not. I suspect an incompativbility between the CPU and the toolchain, maybe related to the bit shift operation (see below). ----- Forwarded message from Clifford Wolf <[email protected]> ----- Date: Thu, 5 Dec 2013 19:16:44 +0100 From: Clifford Wolf <[email protected]> To: Sebastien Bourdeauducq <[email protected]> Subject: Re: Yosys / EHSM Hi Sebastien, On Wed, Dec 04, 2013 at 10:09:17PM +0100, Sebastien Bourdeauducq wrote: > Oh, great! That's awesome :) I have reached a point where I could use your help. Let me quickly summarize what I have done so far and what my problem is: I've spend a significant portion of my day installing diamond_2_2-lm-101-i386-linux.rpm from lattice. after various failed attemts on a couple of distributions I succeded with CentOS 6.5 in a virtual machine. I think this version of the tools is different from the one you are using, because lm32-elf-objcopy from this version does not know "-O verilog". But I was able to simulate the behavior using "-O binary" and hexdump. Now I have something that should be a working testbench. I've compiled the prime number sieve example that I am using for the other CPUs in yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim/blob/master/lm32/sim/sieve.c and this is what I get: DATA WR: @00008180 00000000 (1111) DATA WR: @00008184 00000000 (1111) OUT: 2 DATA RD: @00008180 00000000 DATA RD: @00008184 00000000 OUT: 3 DATA WR: @00008180 00000008 (1111) DATA WR: @00008180 00000008 (1111) DATA WR: @00008184 00000008 (1111) DATA WR: @00008184 00000008 (1111) DATA WR: @00008184 00000008 (1111) OUT: 5 DATA WR: @00008180 00000008 (1111) DATA WR: @00008184 00000008 (1111) OUT: 7 DATA WR: @00008184 00000008 (1111) OUT: 59 OUT: 61 OUT: 67 OUT: 71 OUT: 127 so a lot of prime numbers are missing.. The "DATA RD" and "DATA WR" lines are from my modified test bench and are the reads and writes to the bitmap I use for the sieve. For some reason only one bit gets set in each word. (I assume that lm32 is using a simple write-through cache and thus we see the correct writes.) Maybe something is going wrong with the shift operations? This is all just icarus verilog executing the RTL code. I'll look into the Yosys stuff when the RTL simulation looks ok.. It would be great if you could try to reproduce the problem on your side and see if you could fix it. Reproducing it is easy, you just need the lm32 gnu tools, git and icarus verilog: 1.) check out yosys-bigsim (https://github.com/cliffordwolf/yosys-bigsim) git clone https://github.com/cliffordwolf/yosys-bigsim.git 2.) simulation: cd yosys-bigsim bash scripts/sim_rtl.sh lm32 3.) re-building the application image: cd yosys-bigsim/lm32/sim bash build.sh (note that build.sh internally sets the path to the lm32 gnu tools as installed from diamond_2_2-lm-101-i386-linux.rpm.) on a side note: I've found a bug in your test bench: - assign dmem_we = {4{d_cyc & d_stb & d_we}} & d_sel; + assign dmem_we = {4{d_cyc & d_stb & d_we & ~|d_adr[31:16]}} & d_sel; otherwise it will write to the memory when writing to the uart or the qemu test core. (probably never caused a problem because the lower bits of those addresses map to the boot loader that is not needed after the soc has been booted up.) let me know what your thoughts are. I am committed to make lm32 work with yosys but will only put limited time into making the RTL simulation work.. (the "hello world" example works, btw. but this is not doing enough with the cpu to be a reasonable test case for post synthesis verification, and without a good test case the whole post-synthesis simulation effort is pointless.) yours, - clifford -- Relax, its only ONES and ZEROS! _______________________________________________ Devel mailing list [email protected] https://ssl.serverraum.org/lists/listinfo/devel
