On 12/09/2013 04:26 AM, Robert Jördens wrote: > the second demonstrates what I think is a bug in the signed Signals and > comparison code. But I could not identify the culprit.
Applied and fixed that bug. Came from the fact that -1'sd1 is 1 in Verilog (if the context has more bits)... Sébastien _______________________________________________ Devel mailing list [email protected] https://ssl.serverraum.org/lists/listinfo/devel
